
1.4 Product Family
Introduction
STD110
1-6
SEC ASIC
Sigma-Delta ADC/DAC
VLSI offers high speed and high density, but reduced accuracy for analog
components and reduced signal range (reduced dynamic range). Hence, an
exchange of digital complexity and of resolution in time for resolution in signal
amplitude is needed. So good solution is over-sampling data converter.
Oversampling sigma-delta converter is used in slow speed (audio band)
application because of process limit. It's noise shaping (sigma-delta) feature
make high resolution about max. SND=90~100dB
In ADC path, analog single input is converted to differential signal with anti-alias-
ing filtering through anti-aliasing filter block. And sigma-delta modulator converts
the signal into oversampled noise-shaping 1bit PDM (Pulse Density Modulation).
Following digital decimation filter reject the out of band noise and outputs 16bits
high resolution digital data with down sampled to Fs rate. In DAC path, digital in-
put data is oversampled by interpolation filter and it is converted to noise-shaped
1bit PDM through digital sigma-delta modulator. Analog SC-post-filter rejects the
out of band noise. And anti-image filter rejects sampling images and outputs sin-
gle analog signal with high resolution.
Phase Locked Loop
Samsung’s PLL cores implemented as an analog function provide frequency
multiplication capabilities and enable system designers to synchronize ASIC
chip-level clock networks with a common reference signal.
In the past, designers wishing to incorporate a PLL into a digital design
environment had only two options:
(1) A special mixed-signal process to incorporate analog functions onto the chip
(2) An all digital PLL that can be incorporated into a standard digital process.
However, a mixed-signal process is too expensive to be a feasible solution. On
the other hand digital PLLs typically require huge silicon area and exhibits poor
locking time despite their high accuracy.
Differing from the previous solutions, Samsung's PLL cores can be implemented
on standard digital CMOS process while functioning as an analog PLL.
Samsung's PLL cores:
* Require only a few off-chip passive components for the whole function
* Remove the need for an expensive mixed-signal process
* Provide faster locking time than all digital PLLs
* Present low jitter characteristics
Glossary by Core Families
1. Digital-to-Analog Converter
1. Resolution
- An n-bit binary converter should be able to provide 2
n
distinct and
different analog output values corresponding to the set of n-bit binary words. A
converter that satisfies this criterion is said to have resolution of n bits. The
smallestoutputchangethatcanberesolvedbyalinearDACis2
-n
ofthefull-scale
span.
2.Accuracy
-ErrorofaD/Aconverteristhedifferencebetweentheactualanalog
output and the output that is expected when a given digital code is applied to the
converter. Source of error include gain error, offset error, linearity errors and
noise. Error is usually commensurate with resolution, less than 2
-(n+1)
, or 1/2 LSB
of full scale.