STD110
3-298
SEC ASIC
CTSB/D2/D3/D4/D6/D8/D16
Clock Tree Synthesis Buffers
Logic Symbol
Cell Data
Switching Characteristics
CTSB
(Typical process, 25
°
C, 2.5V, t
R
/t
F
= 0.21ns, SL: Standard Load)
CTSBD2
CTSBD3
Input Load (SL)
CTSBD4
A
0.9
Gate Count
CTSBD4
2.00
CTSB
A
0.8
CTSBD2
A
0.9
CTSBD3
A
0.9
CTSBD6
A
1.7
CTSBD8
A
1.8
CTSBD16
A
3.5
CTSB
1.00
CTSBD2
1.33
CTSBD3
1.67
CTSBD6
2.67
CTSBD8
3.33
CTSBD16
6.33
A
Y
Path
Parameter
Delay [ns]
SL = 2
0.120
0.114
0.167
0.144
<
Delay Equations [ns]
Group1*
0.064 + 0.028*SL
0.056 + 0.029*SL
0.138 + 0.014*SL
0.109 + 0.017*SL
Group2*
0.059 + 0.029*SL
0.050 + 0.030*SL
0.143 + 0.013*SL
0.114 + 0.016*SL
Group3*
0.052 + 0.030*SL
0.045 + 0.031*SL
0.145 + 0.013*SL
0.115 + 0.016*SL
A to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 4, *Group2 : =
Path
Parameter
Delay [ns]
SL = 2
0.087
0.079
0.162
0.139
<
Delay Equations [ns]
Group1*
0.059 + 0.014*SL
0.049 + 0.015*SL
0.145 + 0.009*SL
0.118 + 0.010*SL
Group2*
0.058 + 0.014*SL
0.051 + 0.015*SL
0.151 + 0.007*SL
0.124 + 0.009*SL
Group3*
0.049 + 0.015*SL
0.041 + 0.015*SL
0.158 + 0.007*SL
0.130 + 0.008*SL
A to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 4, *Group2 : =
Path
Parameter
Delay [ns]
SL = 2
0.090
0.080
0.169
0.149
<
Delay Equations [ns]
Group1*
0.075 + 0.007*SL
0.063 + 0.009*SL
0.156 + 0.007*SL
0.134 + 0.007*SL
Group2*
0.066 + 0.010*SL
0.056 + 0.010*SL
0.163 + 0.005*SL
0.140 + 0.006*SL
Group3*
0.056 + 0.010*SL
0.047 + 0.011*SL
0.173 + 0.004*SL
0.148 + 0.006*SL
A to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 4, *Group2 : =
Truth Table
A
0
1
Y
0
1
