
SEC ASIC
3-426
MDL110
LD6Q/LD6QD2
D Latch with Active Low, Reset, Q Output Only, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements
(Typical process, 25
°
C,2.5V, Unit = ns)
Value (ns)
LD6Q
0.303
0.000
0.273
0.250
0.000
0.489
Input Load (SL)
Gate Count
LD6Q
LD6Q
GN
0.6
LD6QD2
GN
0.6
LD6QD2
D
0.6
RN
0.8
D
0.6
RN
0.8
4.00
4.33
Parameter
Symbol
LD6QD2
0.300
0.000
0.275
0.271
0.000
0.448
Input Setup Time (D to GN)
Input Hold Time (D to GN)
Pulse Width Low (GN)
Pulse Width Low (RN)
Recovery Time (RN to GN)
Removal Time (RN to GN)
t
SU
t
HD
t
PWL
t
PWL
t
RC
t
RM
D
GN
Q
RN
GLN
GN
GNB
RN
RN
D
GNB
GLN
Q
RN
GLN
GNB
Truth Table
D
0
1
x
x
GN
0
0
1
x
RN
1
1
1
0
Q (n+1)
0
1
Q (n)
0