參數(shù)資料
| 型號： | SX1506I091TRT |
| 廠商： | Semtech |
| 文件頁數(shù)： | 8/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC GPIO EXP I2C 16CH 28UTQFN |
| 標準包裝： | 1 |
| 接口： | I²C |
| 輸入/輸出數(shù)： | 16 |
| 中斷輸出： | 是 |
| 頻率 - 時鐘： | 400kHz |
| 電源電壓： | 2.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-UFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-QFN-UT（4x4） |
| 包裝： | 標準包裝 |
| 其它名稱： | SX1506I091DKR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
WIRELESS & SENSING
Rev 3 – 16
th May 2012
www.semtech.com
16
SX1504/SX1505/SX1506
4/8/16 Channel GPIO
Master operations
SX1504, SX1505 or SX1506 operations (Slave)
S: Start Condition
Slave Address: 7 bit
W: Write = ‘0’
Register Address: 8 bit
R: Read = ‘1’
Data: 8 bit
A: Acknowledge (sent by slave)
NACK: Non-Acknowledge (sent by master)
Sr: Repeated Start Condition
P: Stop condition
Figure 11 - 2-Wire Serial Interface, Read – Stop Separated Mode Operation
4.6
Interrupt (NINT)
At start-up, the transition detection logic is reset, and NINT is released to a high-impedance state. The interrupt
mask register is set to 0xFF, disabling the interrupt output for transitions on all I/O ports. The transition flags are
cleared to indicate no data changes.
An interrupt NINT can be generated on any programmed combination of I/Os rising and/or falling edges through
the RegInterruptMask and RegSense registers.
If needed, the I/Os which triggered the interrupt can then be identified by reading RegInterruptSource register.
When NINT is low (i.e. interrupt occurred), it can be reset back high (i.e. cleared) by writing 0xFF in
RegInterruptSource (this will also clear corresponding bits in RegEventStatus register).
SX1506 also allows the interrupt to be cleared automatically when reading RegData register (Cf. RegAdvanced)
Example: We want to detect rising edge of I/O[1] on SX1505 (NINT will go low).
1.
We enable interrupt on I/O[1] in RegInterruptMask
RegInterruptMask =“XXXXXX0X”
2.
We set edge sense for I/O[1] in RegSense
RegSenseLow =“XXXX01XX”
4.7
Programmable Logic Functions (PLD)
The SX1504, SX1505 and SX1506 offer a unique fully programmable logic functions like a PLD to give more
flexibility and reduce external logic gates used for standard applications.
Since the whole truth table is fully programmable, the SX1504, SX1505, and SX1506 can implement
combinatory functions ranging from the basic AND/OR gates to the most complicated ones with up to four 3-to1
PLDs or two 3-to-2 PLDs which can also be externally cascaded if needed.
In all cases, any IO not configured for PLD functionality retains its GPIO functionality while I/Os used by the PLD
have their direction automatically set accordingly.
Please note that while RegDir corresponding bits are ignored for PLD operation they may still be set to input to
access unused PLD inputs as normal GPI (PLD truth table can define some inputs to have no effect on PLD
output) and/or generate interrupt based on any of the PLD inputs or outputs bits.
4.7.1
SX1504
The SX1504 I/Os can be configured to provide any combinational 2-to-1 logic function using I/O[0-2] whilst
retaining GPIO capability on I/O[3] OR provide a combinational 3-to-1 decode function using all 4 I/O ports.
RegPLDMode
SX1504 I/Os
1:0
3
2
1
0
00
GPIO
01
GPIO
PLD OUT PLD IN
PLD IN
10
PLD OUT PLD IN
PLD IN
Table 7 – SX1504 PLD Modes Settings
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