1998 Feb 16
10
Philips Semiconductors
Product specification
QIC digital equalizer
SZA1000
CONTROL REGISTER
Control register settings
The control register is accessible through the serial interface and contains 46 8-bit entries as shown in Table 1.
Table 1
Control register
ADDRESS
NAME
DESCRIPTION
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
FIR_VAL0
FIR_VAL1
FIR_VAL2
FIR_VAL3
FIR_VAL4
FIR_VAL5
FIR_VAL7
FIR_VAL8
FIR_VAL9
FIR_SEL05
FIR_SEL16
FIR_SEL27
FIR_SEL38
FIR_SEL49
FIR_SEL10
FIR_SHIFT
LPF_VAL1
LPF_VAL4
LPF_VAL2
LPF_VAL5
LPF_VAL3
LPF_VAL6
LPF_SHIFT
QUAL_FIX_POS
QUAL_FIX_NEG
QUAL_VAR_GAIN
QUAL_SLOPE_DEL
GAP_THRESH
WEQ_SET0
WEQ_SET1
WEQ_CLK_DIV
IDAC1
IDAC2
FIR tap 0 coefficient value (see Table 2)
FIR tap 1 coefficient value
FIR tap 2 coefficient value
FIR tap 3 coefficient value
FIR tap 4 coefficient value
FIR tap 5 coefficient value
FIR tap 6 coefficient value
FIR tap 7 coefficient value
FIR tap 8 coefficient value
FIR tap 9 coefficient value
FIR tap positions (see Tables 3 and 4)
FIR tap positions
FIR tap positions
FIR tap positions
FIR tap positions
FIR tap positions
FIR output scaling (see Table 5)
LPF tap coefficient value (see Table 6)
LPF tap coefficient value
LPF tap coefficient value
LPF tap coefficient value
LPF tap coefficient value
LPF tap coefficient value
LPF output scaling (see Table 8)
Amplitude qualifier positive fixed qualification threshold
Amplitude qualifier negative fixed qualification threshold
Amplitude qualifier variable gain factors (see Tables 9 and 12)
Amplitude detector slope qualification delay (see Table 10)
Gap detector fixed threshold
WEQ settings (see Tables 13 and 14)
WEQ settings (see Tables 15, 16 and 17)
WEQ clock divider (see Tables 18 and 19)
not used
IO1 DAC current (see Table 20)
IO2 DAC current (see Table 20)