參數(shù)資料
型號(hào)： SZA1000H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： QIC digital equalizer
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
文件頁數(shù)： 21/32頁
文件大?。?/td> 164K
代理商： SZA1000H
1998 Feb 16
21
Philips Semiconductors
Product specification
QIC digital equalizer
SZA1000
Table 42
Proportional gain factor KP
M
AXIMUM LIKELIHOOD DETECTOR FUNCTIONS
Address 45: Settings
Table 43
Address 45: MLD_SET
Notes
1.
Check for k constraint: k is the maximum number of channel bit-cells allowed without a transition. For MFM code:
k = 3 (ks = 4), for RLL(1,7) code: k = 7 (ks = 8).
Check for d = 1 constraint: d is the minimum number of channel bit-cells without transitions that must come between
two bit cells with transitions. d = 1 for both MFM and RLL(1,7) codes
3. Check partial response constraints; delete incorrect peaks.
4. Check partial response constraints; add missing peaks.
5. ks = k + 1.
2.
S
TATUS REGISTER
The status register contains 5 status bytes. The contents of the status bytes can be read via the serial interface.
Table 44
Status bytes; notes 1 to 4
Notes
1.
The levels are measured behind the re-sampling block (interpolator) (see Fig.1).
2.
Actual PLL frequency is an 8-bit unsigned number:
3.
4.
LEVEL_FIL can be used for reading of the burst levels, or in an AGC loop (with the TZA1000 preamplifier).
LEVEL_POS, LEVEL_NEG, LEVEL_ABS and LEVEL_FIL are 8-bit numbers in two’s complement format.
NP
KP
0
1
2
3
4
5
6
7
1
1
2
1
4
1
8
1
16
1
32
D7
D6
D5
D4
D3
ks3
(5)
D2
ks2
(5)
D1
ks1
(5)
D0
ks0
(5)
en_k
(1)
en_d
(2)
PR1
(3)
PR0
(4)
ADDRESS
DATA
NAME
DESCRIPTION
255
255
255
255
255
0
1
2
3
4
FREQ
actual frequency of PLL
positive peaks in measured level
negative peaks in measured level
measured peak-to-peak level
low-pass filtered LEVEL_ABS
LEVEL_POS
LEVEL_NEG
LEVEL_ABS
LEVEL_FIL
f
s
F256
×
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