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參數(shù)資料
| 型號(hào)： | SZA1000H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | QIC digital equalizer |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 164K |
| 代理商： | SZA1000H |
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1998 Feb 16
11
Philips Semiconductors
Product specification
QIC digital equalizer
SZA1000
Control register functions
Control register functions are detailed in Tables 2 to 43.
FIR
FUNCTION
Addresses 0 to 9: FIR tap coefficient values
Table 2
Coefficient values: FIR_VAL0 to FIR_VAL9; note 1
Note
1.
These are 7-bit coefficient values in two’s complement notation; taps 5 to 9 are only used when R = 2; tap 10 has a
fixed coefficient value of +64.
Addresses 10 to 15: FIR tap position selection
Table 3
Tap position selection: FIR_SELnn; note 1
Note
1.
See Table 4 for the value of FSn.n.
35
EQ MODE0
Mode setting for PACLK (pin 29) and GAP/STRIPE (pin 21)
(see Tables 21, 22 and 23)
differentiator settings (see Tables 24, 25 and 26)
main clock divider (see Tables 27 and 28)
stripe detector nominal frequency (see Table 29)
equalizer mode settings
PLL nominal frequency bits 0 to 7
PLL nominal frequency bits 8 to 10
PLL window shift
PLL loop filter integrating gain and range
PLL loop filter proportional gain
maximum likelihood detector settings
36
37
38
39
40
41
42
43
44
45
DIFF
CLK_DIV
STRIPE_F
EQ_MODE1
PLL_FREQL
PLL_FREQH
WIN_SHIFT
PLL_NI
PLL_NP
MLD_SET
D7
D6
D5
D4
D3
D2
D1
D0
FIR_VALn.6
FIR_VALn.5
FIR_VALn.4
FIR_VALn.3
FIR_VALn.2
FIR_VALn.1
FIR_VALn.0
ADDR.
NAME
TAPS
D7
D6
D5
D4
D3
D2
D1
D0
10
11
12
13
14
15
FIR_SEL05
FIR_SEL16
FIR_SEL27
FIR_SEL38
FIR_SEL49
FIR_SEL10
0 and 5
1 and 6
2 and 7
3 and 8
4 and 9
10
FS0.2
FS1.2
FS2.2
FS3.2
FS4.2
FS0.1
FS1.1
FS2.1
FS3.1
FS4.1
FS0.0
FS1.0
FS2.0
FS3.0
FS4.0
FS10.3 FS10.2 FS10.1 FS10.0
FS5.2
FS6.2
FS7.2
FS8.2
FS9.2
FS5.1
FS6.1
FS7.1
FS8.1
FS9.1
FS5.0
FS6.0
FS7.0
FS8.0
FS9.0
ADDRESS
NAME
DESCRIPTION
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