1998 Aug 26
18
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
12 TIMER/EVENT COUNTERS
The SZF2002 contains three 16-bit timer/event counter
registers; Timer 0, Timer 1 and Timer 2 which can perform
the following functions:
Measure time intervals and pulse duration
Count events
Generate interrupt requests.
In the ‘Timer’ operating mode the register increments
every machine cycle. Since a machine cycle consists of
6 clock periods, the count rate is
1
6
f
clk
.
In the ‘Counter’ operating mode, the register increments in
response to a HIGH-to-LOW transition. Since it takes
2 machine cycles (12 clock periods) to recognize a
HIGH-to-LOW transition, the maximum count rate is
1
12
f
clk
. To ensure a given level is sampled, it should be
held for at least one complete machine cycle.
12.1
Timer 0 and Timer 1
Timer 0 and Timer 1 can be programmed independently to
operate in four modes:
Mode 0 8-bit timer or 8-bit counter each with divide-by-32
prescaler.
Mode 1 16-bit time-interval or event counter.
Mode 2 8-bit time-interval or event counter with automatic
reload upon overflow.
Mode 3 Timer 0 establishes TL0 and TH0 as two
separate counters.
12.2
Timer 2
Timer 2 is a 16-bit timer/up-down counter that can operate
(like Timer 0 and 1) either as a timer or as an event
counter. These functions are selected by the state of the
C/T2 bit in the T2CON register; see Section 12.3.
Three operating modes are available: Capture,
Auto-reload and Baud Rate Generator, which also are
selected via the T2CON register.
12.2.1
C
APTURE MODE
Figure 9 shows the Capture mode. Two options in this
mode may be selected by the EXEN2 bit in T2CON:
If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter
that sets the Timer 2 overflow bit (TF2) on overflow, this
can be used to generate an interrupt.
If EXEN2 = 1, Timer 2 operates as already described
but with the additional feature that a HIGH-to-LOW
transition at external input T2EX causes the current
value in TL2 and TH2 to be captured into registers
RCAP2L and RCAP2H respectively. In addition, the
transition at T2EX causes the EXF2 bit in T2CON to be
set; this may also be used to generate an interrupt.
12.2.2
A
UTO
-
RELOAD MODE
Figure 10 shows the Auto-reload mode.
Counting up (DCEN = 0)
In the Auto-reload mode and counting up, registers
RCAP2L/RCAP2H are used to hold a reload value for
TL2 /TH2 when Timer 2 rolls over. By setting/clearing bit
EXEN2 in T2CON the external trigger input pin T2EX
can be enabled/disabled. If EXEN2 = 0, then Timer 2 is
a 16-bit timer/counter which upon overflow sets TF2,
and reloads TL2/TH2 with the reload value held in
RCAP2L/RCP2H. If EXEN2 = 1, then Timer 2 performs
as above, but with the added feature that a
HIGH-to-LOW transition at pin T2EX causes the current
Timer 2 value (TL2/TH2 data) to be reloaded with the
value held in RCAP2L/RAP2H, and bit EXF2 in T2CON
to be set.
Timer 2 interrupt will be set if EXF2 is set or TF2 is set.
Counting up (DCEN = 1 and T2EX = 1).
In this mode
Timer 2 will count up. When the timer overflows (FFFFH
state), TF2 bit will be set. This will reload TL2 and TH2
with the contents of T2CAPL and T2CAPH, respectively.
Also bit EXF2 will be toggled. Bit EXF2 can be used as
the 17th bit if desired.
Timer 2 interrupt will be set only if TF2 is set.
Counting down (DCEN = 1 and T2EX = 0.
In this mode
Timer 2 will be counting down. Underflow will occur
when the contents of TL2/TH2 matches the contents of
RCAP2L/RCAP2H. A Timer 2 roll-over from
0000H to FFFFH is not considered as an underflow.
Upon underflow, bit TF2 will be set and registers
TL2/TH2 will be loaded with FFFFH. In addition, an
underflow will cause bit EXF2 to toggle, such that it can
be used as the 17th bit if desired.
Timer 2 interrupt will be set only if TF2 is set.
12.2.3
B
AUD
R
ATE
G
ENERATOR MODE
The Baud Rate Generator mode is selected when
RCLK0 = 1 or TCLK0 = 1 or RCLK1 = 1 or TCLK1 = 1.
It will be described in conjunction with the serial port
(UART); see Section 17.3.2.