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| 型號： | SZF2002 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage 8-bit microcontroller with 6-kbyte embedded RAM(帶6K字節(jié)嵌入RAM的低壓8位微控制器) |
| 中文描述： | 低電壓8位微控制器與6嵌入式RAM字節(jié)（帶6清音字節(jié)嵌入內(nèi)存的低壓8位微控制器） |
| 文件頁數(shù)： | 25/76頁 |
| 文件大?。?/td> | 431K |
| 代理商： | SZF2002 |
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1998 Aug 26
25
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
14 ANALOG-TO-DIGITAL CONVERTER (ADC)
The analog input circuitry consists of a 6-input analog
multiplexer and an ADC with 8-bit resolution. The analog
supply (V
DDA
) and analog ground (V
SSA
) are connected via
separate input pins. For clock frequencies higher than
8 MHz the clock prescaler is needed (divide-by-2).
The functional diagram of the ADC is shown in Fig.14.
The ADC is controlled using the ADC Control Register
(ADCON). Input channels are selected by the analog
multiplexer via the ADCON register bits AADR0 to AADR2.
A conversion is started by setting the ADCS bit in the
ADCON register. The completion of the 8-bit ADC
conversion is flagged by ADCI in the ADCON register,
which will generate an interrupt if this is enabled (EAD).
The result is stored in the Special Function Register ADCH
(address C5H).
To save power the ADC current is switched on only during
conversion and is independent of the processor mode
(active, Idle or Power-down). If the processor goes into Idle
or Power-down mode, the ADC interrupt must be used to
wake-up the CPU again.
While ADCS = 1 or ADCI = 1, a new ADC start will be
blocked and consequently lost, however an ADC
conversion already in progress will finish uninterrupted.
An ADC conversion already in progress is aborted when
the Power-down mode is entered. The result of a
completed conversion (ADCI = 1) remains unaffected
when entering the Idle or Power-down mode.
When no result of a completed conversion (ADCI = 0) is
available, the ADCON and ADCH registers will be reset
when entering the Power-down mode. Note that AADRx
and CKDIV have to be set explicitly to restore their
previous values for the first conversion after Power-down
mode.
Table 14
Conversion time in clock cycles
CONDITION
f
clk
≤
8 MHz,
CKDIV = 0
f
clk
> 8 MHz,
CKDIV = 1
MAX.
REMARK
288
normal conversion
576
prescaler used
Fig.14 Functional diagram of analog input.
(1) For the descriptions of ADCON bits see Table 16.
handbook, full pagewidth
MGM187
ANALOG INPUT
MULTIPLEXER
8-BIT ADC
(succesive approximation)
ADCON
(1)
1
2
3
4
5
6
7
0
1
2
3
4
5
6
Power-down
7
0
VDDA
VSSA
ADCH
INTERNAL BUS
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
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