參數(shù)資料
型號(hào): SZF2002
廠商: NXP Semiconductors N.V.
英文描述: Low voltage 8-bit microcontroller with 6-kbyte embedded RAM(帶6K字節(jié)嵌入RAM的低壓8位微控制器)
中文描述: 低電壓8位微控制器與6嵌入式RAM字節(jié)(帶6清音字節(jié)嵌入內(nèi)存的低壓8位微控制器)
文件頁(yè)數(shù): 20/76頁(yè)
文件大?。?/td> 431K
代理商: SZF2002
1998 Aug 26
20
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
12.3
Timer/Counter 2 Control Register (T2CON)
Table 6
Timer/Counter 2 Control Register (SFR address C8H)
Table 7
Description of T2CON bits
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK0
TCLK0
EXEN2
TR2
C/T2
CP/RL2
BIT
SYMBOL
DESCRIPTION
7
TF2
Timer 2 overflow flag.
Set by a Timer 2 underflow or overflow and must be cleared by
software. TF2 will not be set when in either the Baud Rate generation mode or Clock out
mode.
Timer 2 external flag.
Set when either a capture or reload is caused by a negative
transition on T2EX and when EXEN2 = 1. In Auto-reload mode it is toggled on an
underflow or overflow. Cleared by software.
Receive clock 0 flag.
When set, causes the UART to use Timer 2 overflow pulses.
RCLK0 = 0, causes Timer 1 overflow pulses to be used.
Transmit clock 0 flag.
When set, causes the UART to use Timer 2 overflow pulses.
TCLK0 = 0, causes Timer 1 overflow pulses to be used.
Timer 2 external enable flag.
When set, allows a capture or reload to occur, together
with an interrupt, as a result of a negative transition on input T2EX (if in Capture mode
or Auto-reload mode with DCEN reset). If in Auto-reload mode and DCEN is set, this bit
has no influence. In the other modes EXF2 is set and an interrupt is generated on a
HIGH-to-LOW transition on T2EX pin. In all modes EXEN2 = 0, causes Timer 2 to
ignore events at T2EX.
Timer 2 start/stop control.
When TR2 = 1, Timer 2 is started.
Timer or counter select for Timer 2.
C/T2 = 0, selects the internal timer with a clock
frequency of
1
6
f
clk
. C/T2 = 1, selects the external event counter; negative edge
triggered.
Capture/Reload flag.
Selection of Capture or Auto-reload mode.
6
EXF2
5
RCLK0
4
TCLK0
3
EXEN2
2
1
TR2
C/T2
0
CP/RL2
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