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| 型號(hào)： | SZF2002 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage 8-bit microcontroller with 6-kbyte embedded RAM(帶6K字節(jié)嵌入RAM的低壓8位微控制器) |
| 中文描述： | 低電壓8位微控制器與6嵌入式RAM字節(jié)（帶6清音字節(jié)嵌入內(nèi)存的低壓8位微控制器） |
| 文件頁數(shù)： | 46/76頁 |
| 文件大?。?/td> | 431K |
| 代理商： | SZF2002 |
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1998 Aug 26
46
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
18 INTERRUPT SYSTEM
External events and the real-time-driven on-chip
peripherals require service by the CPU asynchronously to
the execution of any particular section of code. To tie the
asynchronous activities of these functions to normal
program execution a multiple-source, two-priority-level,
nested interrupt system is provided. The SZF2002
acknowledges interrupt requests from fifteen sources as
follows:
INT0 to INT8
Timer 0, Timer 1 and Timer 2
I
2
C-bus serial I/O
UART
ADC.
Each interrupt vectors to a separate location in program
memory for its service routine. Each source can be
individually enabled or disabled by corresponding bits in
the Interrupt Enable Registers (IEN0 and IEN1).
The priority level is selected via the Interrupt Priority
Registers (IP0 and IP1). All enabled sources can be
globally disabled or enabled. Figure 25 shows the interrupt
system.
18.1
External interrupts INT2 to INT8
Port 1 lines serve an alternative purpose as seven
additional interrupts INT2 to INT8. When enabled, each of
these lines (as well as INT0 and INT1) may wake-up the
device from the Power-down mode. Using the Interrupt
Polarity Register (IX1), each pin may be initialized to be
either active HIGH or active LOW. IRQ1 is the Interrupt
Request Flag Register. If the interrupt is enabled, each flag
will be set on an interrupt request but must be cleared by
software, i.e. via the interrupt software or when the
interrupt is disabled.
A low priority interrupt can be interrupted by a high priority
interrupt but not by another low priority interrupt. A high
priority interrupt routine can not be interrupted by any other
interrupt. If two interrupt requests of different priority levels
are received simultaneously, the request having the
highest priority level will be serviced. If interrupt requests
of the same priority level are received simultaneously an
internal polling sequence determines which request is
serviced. Thus within each priority level there is a second
priority structure determined by the polling sequence (see
Fig.25).
Port 1 interrupts are level sensitive. A Port 1 interrupt will
be recognized when a level (longer than 2 machine cycles,
HIGH or LOW, depending on the Interrupt Polarity
Register) on P1.n is made. The interrupt request is not
serviced until the next machine cycle. Figure 26 shows the
external interrupt system.
18.2
Interrupt priority
Each interrupt source can be set to either a high priority or
to a low priority. If interrupts of the same priority are
requested simultaneously, the processor will branch to the
interrupt polled first, according to Table 36.
A low priority interrupt routine can only be interrupted by a
high priority interrupt. A high priority interrupt routine can
not be interrupted.
Table 36 shows the interrupt vectors in order of priority.
The vector indicates the ROM location where the
appropriate interrupt service routine starts.
Table 36
Interrupt vectors
SYMBOL
VECTOR
ADDRESS
(HEX)
SOURCE
X0 (highest)
S1
X5
T0
T2
X6
X1
X2
X7
T1
X3
X8
SO
X4
ADC (lowest)
0003
002B
0053
000B
0033
005B
0013
003B
0063
001B
0043
006B
0023
004B
0073
external interrupt 0
I
2
C-bus port
external interrupt 5
Timer 0
Timer 2
external interrupt 6
external interrupt 1
external interrupt 2
external interrupt 7
Timer 1
external interrupt 3
external interrupt 8
UART
external interrupt 4
ADC
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