- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361344 > T431616E-7CG (TM Technology, Inc.) 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號： | T431616E-7CG |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| 中文描述： | 100萬× 16內(nèi)存為512k × 16Bit的X 2Banks同步DRAM |
| 文件頁數(shù)： | 7/74頁 |
| 文件大小： | 781K |
| 代理商： | T431616E-7CG |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁
TE
CH
tm
T431616D/E
TM Technology Inc. reserves the right
P. 7
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto precharge function may
be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end
of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank too. The
interrupt coming from the Read command can occur on any clock cycle following a previous Read command
(refer to the following figure).
The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks earlier (i.e.
CLK
COMMAND
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
T0
T 1
T2
T3
T4
T5
T6
T7
T8
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Read Interrupted by a Read
(Burst Length = 4, CAS# Latency = 1, 2, 3)
a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior to the Write command
to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with high-
impedance on the DQ pins must occur between the last read data and the Write command (refer to the following
three figures). If the data output of the burst read occurs at the second clock of the burst write, the
LDQM/UDQM must be asserted (HIGH) at least one clock prior to the Write command to avoid internal bus
contention.
The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
CLK
DQM
COMMAND
DQ's
T0
T 1
T2
T3
T4
T5
T6
T7
T8
NOP
DOUT A0
DINB0
DINB1
DINB2
Must be Hi-Z before
the Write Command
: "H" or "L"
Read to Write Interval
(Burst Length
≥
4, CAS# Latency = 3)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T431616E-7S | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616E-7SG | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T436416A | 4M X 16 SDRAM |
| T436416A-10S | 4M X 16 SDRAM |
| T436416A-10SG | Terminal Block End Barrier; For Use With:AB1 Series Terminal Blocks; Accessory Type:End Barrier; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T431616E-7S | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616E-7SG | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T4322 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIANGULAR TYPE |
| T4323 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIANGULAR TYPE |
| T4333 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIANGULAR TYPE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。