參數(shù)資料
型號(hào): T7570
元件分類: Codec
英文描述: T7570 Programmable PCM Codec with Hybrid-Balance Filter
中文描述: T7570可編程PCM編解碼器與混合平衡濾波器
文件頁數(shù): 21/28頁
文件大?。?/td> 567K
代理商: T7570
21
Lucent Technologies Inc.
Data Sheet
October 1996
T7570 Programmable PCM Codec
with Hybrid-Balance Filter
Timing Characteristics
(continued)
Table 20. PCM Interface Timing
(See Figures 4 and 5.)
Symbol
fBCLK
Parameter
Test Conditions
T
A
(
°
C)
Min
64
Max
4096
Unit
kHz
Frequency of BCLK (can vary
from 64 kHz to 4096 kHz in
8 kHz increments)
Time of BCLK High
Time of BCLK Low
Rise Time of BCLK
Fall Time of BCLK
Hold Time, BCLK Low
FS
X/R
to High or Low
Setup Time FS
X/R
,
High to BCLK Low
Delay Time, BCLK High
to Data Valid
Delay Time, BCLK Low to
D
X
0/1 Disabled if FS
X
Low,
FS
X
Low to D
X
0/1 Disabled if
Eighth BCLK Low, or BCLK
High to D
X
0/1 Disabled if FS
X
High
tBCHBCL
tBCLBCH
tBCH1BCH2
tBCL2BCL1
tBCLFXL
tBCLFRL
tFXHBCL
tFRHBCL
tBCHDXV
Measured from V
IH
to V
IH
Measured from V
IL
to V
IL
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
80
80
30
30
30
ns
ns
ns
ns
ns
30
ns
Load = 100 pF plus two
LSTTL loads
90
ns
tBCLDXZ
–40 to 0
0 to 85
10
15
80
80
ns
ns
tBCHTXL
Delay Time, BCLK High to
Low if FS
X
High, or FS
X
High
to
High-impedance Time, BCLK
Low to
or FS
X
BCLK High to
High if FS
X
High
Delay Time, FS
X/R
High to Data Valid
X
X
Low if BCLK High
Load = 100 pF plus two
LSTTL loads
60
ns
tBCLTXH
X
High if FS
X
Low,
X
15
60
ns
tFXHDXV
Load = 100 pF plus two
LSTTL loads, applies if FS
X/R
rises later than BCLK rising
edge in nondelayed-data
mode only
80
ns
tDRVBCL
Setup Time, D
R
0/1
Valid to BCLK Low
Hold Time, BCLK Low to D
R
0/1
Invalid
BCLK Low to MCLK High at the
End of the First Data Bit
Period
30
ns
tBCLDRX
–40 to 0
0 to 85
15
20
50
ns
ns
ns
tBCLMCH
TS
TS
TS
TS
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