參數(shù)資料
型號(hào)： T7570
元件分類(lèi)： Codec
英文描述： T7570 Programmable PCM Codec with Hybrid-Balance Filter
中文描述： T7570可編程PCM編解碼器與混合平衡濾波器
文件頁(yè)數(shù)： 8/28頁(yè)
文件大小： 567K
代理商： T7570
8
Lucent Technologies Inc.
T7570 Programmable PCM Codec
with Hybrid-Balance Filter
Data Sheet
October 1996
Functional Description
(continued)
Programmable Functions
(continued)
Control Register Instruction
(continued)
Table 3. Control Register Byte 2 Functions
* State at powerup initialization (bit 4 = 0).
Table 4. Coding Law Conventions
Note: The MSB is always the first PCM bit shifted in or out of the T7570.
Bit Number and Name
5
4
MA
IA
—
—
—
—
—
—
—
—
0
X
1
0
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Function
7
F
1
0
0
1
1
—
—
—
—
—
—
—
—
—
—
6
F
0
0
1
0
1
—
—
—
—
—
—
—
—
—
—
3
2
1
0
DN
—
—
—
—
—
—
—
0
1
—
—
—
—
—
DL
—
—
—
—
—
—
—
—
—
0
1
0
—
—
AL
—
—
—
—
—
—
—
—
—
0
X
1
—
—
PP
—
—
—
—
—
—
—
—
—
—
—
—
0
1
Reserved
MCLK = 1.536 MHz or 1.544 MHz
MCLK = 2.048 MHz*
MCLK = 4.096 MHz
μ
-law*
A-law, Including Even Bit Inversion
A-law, No Even Bit Inversion
Delayed Data Timing
Nondelayed Data Timing*
Normal Operation*
Digital Loopback
Analog Loopback
Power Amp Enabled in Powerdown
Power Amp Disabled in Powerdown*
V
IN
μ
-Law
MSB LSB
10000000
11111111
00000000
True A-Law With
Even Bit Inversion
MSB LSB
10101010
11010101
00101010
A-Law Without
Even Bit Inversion
MSB LSB
111111111
10000000
01111111
V
IN
= + Full Scale
V
IN
= 0 V
V
IN
= – Full Scale
Master Clock Frequency Selection
A master clock must be provided to the T7570 for oper-
ation of the filter and coding/decoding functions. The
MCLK frequency must be either 1.536 MHz,
1.544 MHz, 2.048 MHz, or 4.096 MHz and must be
synchronous with BCLK at the start of each frame. Bits
F
0
and F
1
(see Table 3) must be set during initialization
to select the correct internal divider.
Coding Law Selection
Bits MA and IA in Table 3 permit the selection of
μ
-law
coding or A-law coding, with or without even bit inver-
sion.
Analog Loopback
The analog loopback mode is entered by setting the AL
and DL bits in the control register as shown in Table 3.
In the analog loopback mode, the transmit input VF
X
I is
isolated from the input pin and internally connected to
the VF
R
O output, forming a loop from the receive PCM
register back to the transmit PCM register. The VF
R
O
pin remains active, and the programmed settings of the
transmit and receive gains remain unchanged; there-
fore, care must be taken to ensure that overload levels
are not exceeded anywhere in the loop. It is recom-
mended that the hybrid-balance filter be disabled dur-
ing analog loopback.
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