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參數(shù)資料
| 型號： | T7570 |
| 元件分類： | Codec |
| 英文描述： | T7570 Programmable PCM Codec with Hybrid-Balance Filter |
| 中文描述： | T7570可編程PCM編解碼器與混合平衡濾波器 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 567K |
| 代理商： | T7570 |
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4
Lucent Technologies Inc.
T7570 Programmable PCM Codec
with Hybrid-Balance Filter
Data Sheet
October 1996
Pin Information
(continued)
Table 1. Pin Description
Pin
1
2
Symbol
GND
VF
Type
—
O
Name/Description
Ground
Receive Analog Power Amplifier Output.
as 300
. PCM data received on the assigned D
output as a voice-frequency signal.
No Connect.
Connections may be made to or traces may be routed through this pin.
No Connects.
Do not make connections to or route traces through pins 4 and 5.
. All analog and digital signals are referenced to this pin.
R
O
This pin can drive load impedances as low
R
pin is decoded and appears at this
3
4
5
6
7
NC
NC
—
—
IL3
IL2
I/O
I/O
Interface Latch I/O.
as determined by the state of the corresponding bits in the latch direction register
(LDR). For pins configured as inputs, the logic state sensed on each input is latched
into the interface latch register (ILR) whenever control data is written to the T7570, and
the information is shifted out on the CO pin. When configured as outputs, control data
written into the ILR appears at the corresponding IL pins.
Receive Frame-Sync Input.
A pulse or square-wave waveform with an 8 kHz repeti-
tion rate is applied to this input to define the start of the receive time slot assigned to
this device (nondelayed frame mode), or the start of the receive frame (delayed frame
mode using the internal time-slot assignment counter).
Receive PCM Inputs.
These receive data input(s) are inactive except during the
assigned receive time slot of the assigned port when the receive PCM data is shifted in
on the falling edges of BCLK.
Control Output.
Serial control information is shifted out from the T7570 on this pin
when
is low. It can be connected to CI if required.
CS
These pins can be individually programmed as inputs or outputs
8
FS
R
I
9
10
D
D
R
1
0
R
I
I
11
CO
O
12
CI
I
Control Input.
is low. It can be connected to CO if required.
Control Clock.
This clock shifts serial control information into CI or out from CO when
the
is low, depending on the current instruction. CCLK can be asynchronous with
the other system clocks.
Chip Select (Active-Low).
When this pin is low, control information can be written into
or read from the T7570 via the CI and CO pins.
Master Reset.
This logic input must be pulled low for normal operation of the T7570.
When pulled momentarily high (at least 1
μ
s), all programmable registers in the device
are reset to the states specified under powerup initialization.
Bit Clock Input.
This pin shifts PCM data into and out of the D
can vary from 64 kHz to 4.096 MHz in 8 kHz increments and must be synchronous with
MCLK at the start of each frame. MCLK can be used as BCLK.
Master Clock.
The master-clock input is used by the switched capacitor filters and the
encoder and decoder sequencing logic. It must be 1.536 MHz, 1.544 MHz,
2.048 MHz, or 4.096 MHz and must be synchronous with BCLK at the start of each
frame.
Transmit PCM Output.
These transmit-data, high-impedance state outputs remain in
the high-impedance state except during the assigned transmit time slot on the
assigned port, during which the transmit PCM data byte is shifted out on the rising
edges of BCLK.
Backplane Line Driver Enable (Active-Low).
floating in a high-impedance state. When a time slot is active on one of the D
the appropriate
X
output pulls low to enable a backplane line driver.
TS
Serial control information is shifted into the T7570 on this pin when
13
CCLK
I
14
I
15
MR
I
16
BCLK
I
R
and
D
X
pins. BCLK
17
MCLK
I
18
19
D
D
X
0
1
X
O
O
20
21
X
0
1
X
O
O
Normally, these open-drain outputs are
X
outputs,
CS
CS
CS
TS
TS
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