參數(shù)資料
型號(hào)： T7570
元件分類： Codec
英文描述： T7570 Programmable PCM Codec with Hybrid-Balance Filter
中文描述： T7570可編程PCM編解碼器與混合平衡濾波器
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 567K
代理商： T7570
9
Lucent Technologies Inc.
Data Sheet
October 1996
T7570 Programmable PCM Codec
with Hybrid-Balance Filter
Functional Description
(continued)
Programmable Functions
(continued)
Digital Loopback
The digital loopback mode is entered by setting the AL
and DL bits in the control register as shown in Table 3.
This mode provides another stage of path verification
by enabling data written into the receive PCM register
to be read back from that register in any transmit time
slot at D
X
0/1. In digital loopback mode, the decoder
remains functional and outputs a signal at VF
R
O. If this
is undesirable, the receive output can be disabled by
programming the receive gain register to all 0s.
Interface Latch Directions
Immediately following powerup, all interface latches
assume they are inputs and, therefore, all IL pins are in
a high-impedance state. Each IL pin can be individually
programmed as a logic input or output by writing the
appropriate instruction to the LDR (see Tables 2 and 5).
For minimum power dissipation, unconnected latch
pins should be programmed as outputs.
Bits L
5
—L
0
must be set by writing the specified instruc-
tion to the LDR with the L bits in the second byte set as
follows.
Table 5. Byte 2 Functions of Latch Direction
Register
Note: X = don't care.
Interface Latch States
Interface latches configured as outputs assume the
state determined by the appropriate data bit in the
2-byte instruction written to the interface latch register
(ILR) as shown in Tables 2 and 6. Latches configured
as inputs sense the state applied by an external
source, such as the off-hook detect output of a SLIC.
All bits of the ILR, i.e., sensed inputs and the pro-
grammed state of outputs, can be read back in the sec-
ond byte of a read of the ILR.
It is recommended that during initialization, the state of
IL pins to be configured as outputs should be pro-
grammed first, followed immediately by the LDR.
Table 6. Interface Latch Data Bit Order Bit Number
Time-Slot Assignment
The T7570 can operate in either fixed time-slot or time-
slot assignment mode for selecting the transmit and
receive PCM time slots. Following powerup, the device
is automatically in nondelayed timing mode, in which
the time slot always begins with the leading (rising)
edge of frame-sync inputs FS
X
and FS
R
. Time-slot
assignment can only be used with delayed-data timing
(see Figure 5). FS
X
and FS
R
can have any phase rela-
tionship with each other in BCLK period increments.
Alternatively, the internal time-slot assignment counters
and comparators can be used to access any time slot
in a frame by using the frame-sync inputs as marker
pulses for the beginning of transmit and receive time
slots of 8 bits each. A time slot is assigned by a 2-byte
instruction as shown in Tables 2 and 7. The last 6 bits
of the second byte indicate the selected time slot from
0 to 63 using straight binary notation. A new assign-
ment becomes active on the second frame following
the end of the
for the second control byte. The EN
bit allows the PCM inputs, D
R
0/1, or outputs, D
X
0/1, as
appropriate, to be enabled or disabled. Time-slot
assignment mode requires that the FS
X
and FS
R
pulses
must conform to the delayed-data timing format shown
in Figure 5.
Port Selection
Two transmit serial PCM ports, D
X
0 and D
X
1, and two
receive serial PCM ports, D
R
0 and D
R
1, are provided to
enable two-way space switching to be implemented.
Port selections for transmit and receive are made
within the appropriate time-slot assignment instruction
using the PS bit in the second byte. Port selection can
only be used in delayed-data timing mode.
Table 7 shows the format of the second byte of both
transmit and receive time-slot and port assignment
instructions.
Byte 2 Bit Number
5
4
L
2
L
3
7
L
0
6
3
2
1
X
0
X
L
1
L
4
L
5
L
n
Bit
0
1
IL Direction
Input
Output
Bit Number
4
D
3
7
6
5
3
2
1
X
0
X
D
0
D
1
D
2
D
4
D
5
CS
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