參數(shù)資料
型號: T7570
元件分類: Codec
英文描述: T7570 Programmable PCM Codec with Hybrid-Balance Filter
中文描述: T7570可編程PCM編解碼器與混合平衡濾波器
文件頁數(shù): 23/28頁
文件大?。?/td> 567K
代理商: T7570
23
Lucent Technologies Inc.
Data Sheet
October 1996
T7570 Programmable PCM Codec
with Hybrid-Balance Filter
Timing Characteristics
(continued)
Table 21. Serial Control Port Timing
(See Figure 6.)
Table 22. Interface Latch Timing
(See Figure 6.)
Table 23. Master Reset Pin
Symbol
fCCLK
tCCHCCL
tCCLCCH
tCCH1CCH2 Rise Time of CCLK
tCCL2CCL1
Fall Time of CCLK
tCCLCSL
Hold Time, CCLK Low to
CS
Parameter
Test Conditions
Min
160
160
10
Max
2048
50
50
Unit
kHz
ns
ns
ns
ns
ns
Frequency of CCLK
Time of CCLK High
Time of CCLK Low
Measured from V
IH
to V
IH
Measured from V
IL
to V
IL
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
Measured from first CCLK low transition
Low
tCCLCSH
Hold Time, CCLK Low to
High
CS
Measured from eighth CCLK low transition
100
ns
tCSLCCH
Setup Time,
tion to CCLK Low
Transi-
60
ns
tCSHCCH
Setup Time,
tion to CCLK High
Setup Time, CI Data In to
CCLK Low
Hold Time, CCLK Low to
CI Invalid
Delay Time, CCLK High to
CO Data Out Valid
Transi-
50
ns
tCIVCCL
50
ns
tCCLCIX
50
ns
tCCHCOV
Load = 100 pF plus 2 LSTTL loads
80
ns
tCSLCOV
Delay Time,
CO Valid
Low to
Applies only if separate
used for byte 2
80
ns
tCSHCOZ
Delay Time,
CO High Impedance
High to
Applies when
CCLK high
high occurs before ninth
15
80
ns
Symbol
tILXCCL
Parameter
Test Conditions
Min
100
Max
Unit
ns
Setup Time, IL to Eighth
CCLK of Byte 1
Hold Time, IL Valid from
Eighth CCLK Low (byte 1)
Delay Time CCLK 8 of
Byte 2 to IL
Interface latch inputs only
tCCLILX
50
ns
tCCLILV
Interface latch outputs only C
L
= 50 pF
200
ns
Symbol
tMRHRML
Parameter
Min
1
Max
Unit
μ
s
Duration of Master Reset High
CS
CS
CS
CS
CS
CS
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