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參數(shù)資料
| 型號： | T8533 |
| 英文描述： | T8533/34 Quad Programmable Line Card Signal Processor |
| 中文描述： | T8533/34四線卡可編程信號處理器 |
| 文件頁數(shù)： | 2/48頁 |
| 文件大?。?/td> | 890K |
| 代理商： | T8533 |
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Preliminary Data Sheet
July 2001
Signal Processor
T8533/34 Quad Programmable Line Card
2
Agere Systems Inc.
Table of Contents
Contents
Page
Features ......................................................................1
General Description.....................................................1
Functional Description.................................................3
Pin Information ............................................................5
Functional Description...............................................11
Clocking Considerations .........................................11
The Control Interface ..............................................11
Modes ..................................................................11
Protocol................................................................12
Write Command ...................................................14
Read Command...................................................16
Fast Scan Mode...................................................20
Write All Channels................................................23
Reset Functionality .................................................23
Memory Control Mapping.....................................24
Standby Mode.........................................................24
Test Capabilities .....................................................24
Echo Canceller Functionality ..................................25
SLIC Control Capabilities........................................25
Suggested Initialization Procedures........................25
Signal Processing ...................................................26
Absolute Maximum Ratings.......................................26
Operating Ranges ....................................................27
Handling Precautions ................................................27
Electrical Characteristics...........................................27
dc Characteristics ...................................................27
Analog Interface......................................................28
Transmission Characteristics..................................29
Noise Characteristics..............................................31
Distortion and Group Delay.....................................32
Crosstalk.................................................................33
Timing Characteristics...............................................34
Bus Timing Diagrams................................................36
Normal Mode ..........................................................36
Byte-by-Byte Mode .................................................36
PCM Interface.........................................................37
Applications...............................................................44
Outline Diagrams.......................................................45
68-Pin PLCC...........................................................45
64-Pin TQFP...........................................................46
44-Pin PLCC...........................................................47
Ordering Information..................................................48
Figures
Page
Figure 1. Functional Block Diagram, Each Section ....3
Figure 2. 44-Pin PLCC Pin Diagram........................... 5
Figure 3. 68-Pin PLCC Pin Diagram ...........................7
Figure 4. 64-Pin TQFP Pin Diagram ...........................9
Figure 5. Command Frame Format, Master to Slave,
Read or Write Commands .........................13
Figure 6. Command Frame Format, Slave to Master,
Read Commands ......................................13
Figure 7. Write Operation, Normal Mode
(Continuous DCLK) ...................................14
Figure 8. Write Operation, Normal Mode
(Gapped DCLK) .........................................14
Figure 9. Write Operation, Byte-by-Byte Mode
(Continuous DCLK) .................................. 15
Figure 10. Write Operation, Byte-by-Byte Mode
(Gapped DCLK) ...................................... 15
Figure 11. Read Operation, Normal Mode
(Continuous DCLK) ................................ 16
Figure 12. Read Operation, Normal Mode
(Gapped Clock) ...................................... 17
Figure 13. Read Operation, Byte-by-Byte Mode
(Continuous DCLK) ................................ 18
Figure 14. Read Operation, Byte-by-Byte Mode
(Gapped DCLK) ...................................... 19
Figure 15. Fast Scan, Normal Mode
(Continuous DCLK) ................................ 20
Figure 16. Fast Scan, Normal Mode
(Gapped DCLK) ...................................... 21
Figure 17. Fast Scan, Byte-by-Byte Mode
(Continuous DCLK)................................ 22
Figure 18. Fast Scan, Byte-by-Byte Mode
(Gapped DCLK) ...................................... 22
Figure 19. Hardware Reset Procedure .................... 23
Figure 20. Internal Signal Processing ...................... 26
Figure 21. Serial Interface Timing, Normal Mode
(One Byte Transfer Shown) .................... 36
Figure 22. Serial Interface Timing, Byte-by-Byte
Mode (One Byte Transfer and Gapped
DCLK Shown) ......................................... 36
Figure 23. PCM Bus Timing (Diagram Shown has Bit
Offset of Zero and Minimum Width of
FS) .......................................................... 37
Figure 24. POTS Interface ....................................... 44
Tables
Page
Table 1. Pin Assignments, 44-Pin PLCC,
Per-Channel Functions ................................ 5
Table 2. Pin Assignments, 44-Pin PLCC,
Common Functions .................................... 6
Table 3. Pin Assignments, 68-Pin PLCC,
Per-Channel Functions ................................ 7
Table 4. Pin Assignments, 68-Pin PLCC,
Common Functions .................................... 8
Table 5. Pin Assignments, 64-Pin TQFP,
Per-Channel Functions ................................ 9
Table 6. Pin Assignments, 64-Pin TQFP,
Common Functions .................................. 10
Table 7. Bit Assignments for Fast Scan Mode ....... 20
Table 8. dc Characteristics ..................................... 27
Table 9. Analog Interface ....................................... 28
Table 10. Power Requirements .............................. 29
Table 11. Transmission Characteristics ................. 29
Table 12. Per-Channel Noise Characteristics ........ 31
Table 13. Distortion and Group Delay ..................... 32
Table 14. Crosstalk .................................................. 33
Table 15. Timing Characteristics ............................. 34
Table 16. Echo Canceller Characteristics ............... 35
Table 17. Memory Mapping ..................................... 38
Table 18. Control Bit Definition ................................ 39
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