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參數(shù)資料
| 型號： | T8533 |
| 英文描述： | T8533/34 Quad Programmable Line Card Signal Processor |
| 中文描述： | T8533/34四線卡可編程信號處理器 |
| 文件頁數(shù)： | 20/48頁 |
| 文件大?。?/td> | 890K |
| 代理商： | T8533 |
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Preliminary Data Sheet
July 2001
Signal Processor
T8533/34 Quad Programmable Line Card
20
Agere Systems Inc.
Functional Description
(continued)
The Control Interface
(continued)
Fast Scan Mode
The fast scan mode allows a single byte command to read two SLIC control leads for all four channels with a
1-byte reply. This mode significantly speeds up the normal scanning for off-hook, ring trip, and ring ground detec-
tion. This special command sequence allows the controlling microprocessor to fast scan 2 bits in the SLIC control
byte of each of the four channels. The command code is (00000010)
2
, there are no start address or length fields.
The command returns only a single byte of data, formatted as shown in Table 9.
Table 7. Bit Assignments for Fast Scan Mode
The circuit select in the command structure (Figure 5) is not used for this special single-byte command. The rules
for toggling chip select apply as for the read command. Figures 15—18 illustrate normal or byte-by-byte operation
with continuous or gapped DCLKs.
0125
* Provide sufficient wait time to access read data. Provide sufficient DCLK cycles to effectively wait
≥
1.5
μ
s after the second full DCLK cycle
and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between COMMAND and
DATA. The first two DCLK cycles, when CS goes high, processes the command. A wait is then required to access the read data. Two final
DCLK cycles are required to process the read data.
Two or more DCLK cycles are required before the start of a new command frame.
Figure 15. Fast Scan, Normal Mode (Continuous DCLK)
Bit
Reported Status
0 (LSB)
1
2
3
4
5
6
7 (MSB)
Channel 0, bit 0 (ckt a, address 160, bit 0)
Channel 0, bit 1 (ckt a, address 160, bit 1)
Channel 1, bit 0 (ckt b, address 160, bit 0)
Channel 1, bit 1 (ckt b, address 160, bit 1)
Channel 2, bit 0 (ckt c, address 160, bit 0)
Channel 2, bit 1 (ckt c, address 160, bit 1)
Channel 3, bit 0 (ckt d, address 160, bit 0)
Channel 3, bit 1 (ckt d, address 160, bit 1)
1
2
3
CS
DCLK
DI
COMMAND
DATA
4
5
DO
WAIT
≥
1.5
μ
s
0
1
2
3
4
5
6
7
6
7
0
1
2
3
4
5
6
7
0
*
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