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參數(shù)資料
| 型號： | TAS3103DBTRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| 封裝： | GREEN, PLASTIC, TSSOP-38 |
| 文件頁數(shù)： | 24/148頁 |
| 文件大小： | 1247K |
| 代理商： | TAS3103DBTRG4 |
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15
1.5
Ordering Information
TA
PLASTIC
38-PIN TSSOP
(DBT)
0
°C to 70°C
TAS3103DBT
40
°C to 85°C
TAS3103IDBT
1.6
Terminal Functions
TERMINAL
DESCRIPTION
PULLUP/
(2)
NAME
NO.
I/O
TYPE(1)
DESCRIPTION
PULLUP/
DOWN(2)
A_VDDS (3.3 V)
7
PWR
The PWR pin is used to input 3.3-V power to the DPLL and clock oscillator.
This pin can be connected to the same power source used to drive the DVSS
power pin. To achieve low DPLL jitter, this pin should be bypassed to AVSS
with a 0.01-
F capacitor (low ESR preferable).
None
AVDD_BYPASS_CAP
6
PWR
AVDD_BYPASS_CAP is a pinout of the internally regulated 1.8-VDC power
used by the DPLL and crystal oscillator. This pin should be connected to pin 8
with a 0.01-
F capacitor (low ESR preferable). This pin must not be used to
power external devices.
None
AVSS
8
PWR
AVSS is the ground reference for the internal DPLL and oscillator circuitry.
This pin needs to reference the same ground as DVSS power pin. To achieve
low DPLL jitter, ground noise at this pin must be minimized. The availability of
the AVSS pin allows a designer to use optimizing techniques such as star
ground connections, separate ground planes, or other quiet ground
distribution techniques to achieve a quiet ground reference at this pin.
None
CS0
24
I
D
CS0 is the LSB of a 2-bit code used to generate part of an I2C device address
that makes it possible to address four TAS3103 ICs on the same bus without
additional chip select logic. The pulldowns on the inputs select 00 as a default
when neither pin is connected.
Pulldown
CS1
25
I
D
CS1 is the MSB of a 2-bit code used to generate part of an I2C device address
that makes it possible to address four TAS3103 ICs on the same bus without
additional chip select logic.
Pulldown
DVDD_BYPASS_CAP
29
PWR
DVDD_BYPASS_CAP is a pin-out of the internally regulated 1.8-V power
used by all internal digital logic. This pin must not be used to power external
devices. A low ESR capacitor of at least 470 nF should be placed as close to
the device as possible between this pin and pin 28.
None
DVSS
28
PWR
DVSS is the digital ground pin.
None
GPIO0
18
I/O
D
GPIO0 is a general-purpose I/O, controlled by the internal microprocessor
through I2C commands. When in the I2C master mode, GPIO0 serves as a
volume up command for CH1/CH2.
Pullup
GPIO1
19
I/O
D
GPIO1 is a general-purpose I/O, controlled by the internal microprocessor
through I2C commands. When in the I2C master mode, GPIO1 serves as a
volume down command for CH1/CH2.
Pullup
GPIO2
20
I/O
D
GPIO2 is a general-purpose I/O, controlled by the internal microprocessor
through I2C commands. When in the I2C master mode, GPIO2 serves as a
volume up command for CH3.
Pullup
GPIO3
21
I/O
D
GPIO3 is a general-purpose I/O, controlled by the internal microprocessor
through I2C commands. When in the I2C master mode, GPIO3 serves as a
volume down command for CH3.
Pullup
I2CM_S
27
I
D
I2CM_S is a non-latched input that determines whether the TAS3103 acts as
an I2C master or slave. Logic high, or no connection, sets the TAS3103 as an
I2C master device. A logic low sets the TAS3103 as an I2C slave device. As a
master I2C device, the TAS3103 I2C port must have access to an external
EEPROM for input.
Pullup
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| TAS3103EVM | 功能描述:音頻 DSP TAS3103 Eval Mod RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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