參數(shù)資料
型號(hào): TAS3103DBTRG4
廠(chǎng)商: TEXAS INSTRUMENTS INC
元件分類(lèi): 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO38
封裝: GREEN, PLASTIC, TSSOP-38
文件頁(yè)數(shù): 46/148頁(yè)
文件大?。?/td> 1247K
代理商: TAS3103DBTRG4
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)當(dāng)前第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)
17
TERMINAL
PULLUP/
DOWN(2)
DESCRIPTION
NAME
PULLUP/
DOWN(2)
DESCRIPTION
TYPE(1)
I/O
NO.
PWRDN
2
I
D
PWRDN powers down all logic and stops all clocks whenever logic high is
applied. However, the coefficient memory remains stable through a power
down cycle, as long as a reset is not sent after a power down cycle.
Pulldown
REGULATOR_EN
3
I
D
REGULATOR_EN is only used in factory tests. This pin should always be tied
to ground.
None
RST
26
I
D
RST is the master reset input. Applying a logic low to this pin generates a
master reset. The master reset results in all coefficients being set to their
power-up default state, all data memories being cleared, and all logic signals
being returned to their default values.
Pullup
SCLKIN
1
I
D
SCLKIN is the serial audio port (SAP) input data clock. This clock is only used
when the SAP is a slave. In master mode, SCLKOUT1 internally provides the
serial input clock (SCLKOUT1 from a given TAS3103 must not be connected
to SCLKIN on the same TAS3103 chip).
Pulldown
SCLKOUT1
35
O
D
SCLKOUT1 is one of two serial output bit clocks. It is divided from
MCLKI/XTALI in master mode, and SCLKIN in slave mode. Subaddress
control fields determine the divide ratio in both cases. When the serial audio
port is in a master mode, SCLKOUT1 is used to receive incoming serial data
and should be wired to the data source(s) providing data to the SDIN inputs.
None
SCLKOUT2
36
O
D
SCLKOUT2 is one of two serial output bit clocks. It is divided from
MCLKI/XTALI in master mode, and SCLKIN in slave mode. Subaddress
control fields determine the divide ratio in both cases. SCLKOUT2 is always
used to clock out serial data from the three serial SDOUT output data
channels. SCLKOUT2 is provided separately from SCLKOUT1 to allow
discrete in to TDM out and TDM in to discrete out data format conversions
without the use of external glue logic.
Output
SDIN1
14
I
D
SDIN1, SDIN2, SDIN3, and SDIN4 are the four TAS3103 serial data input
ports. All four input ports support four discrete (stereo) data formats. SDIN1 is
the only data input port that also supports eleven time division multiplexed
data formats. All four ports are capable of receiving data with bit rates up to
24.576 MHz.
Pulldown
SDIN2
15
I
D
SDIN2 is one of the four TAS3103 serial data input ports. SDIN2 supports four
discrete (stereo) data formats, and is capable of receiving data with bit rates
up to 24.576 MHz.
Pulldown
SDIN3
16
I
D
SDIN3 is one of the four TAS3103 serial data input ports. SDIN4 supports four
discrete (stereo) data formats, and is capable of receiving data with bit rates
up to 24.576 MHz.
Pulldown
SDIN4
17
I
D
SDIN4 is one of the four TAS3103 serial data input ports. SDIN4 supports four
discrete (stereo) data formats, and is capable of receiving data with bit rates
up to 24.576 MHz.
Pulldown
SDOUT1
30
O
D
SDOUT1, SDOUT2, and SDOUT3 are the three TAS3103 serial data output
ports. All three output ports support four discrete (stereo) data formats.
SDOUT1 is the only data output port that also supports eleven time division
multiplexed data formats. All three ports are capable of outputting data at bit
rates up to 24.576 MHz.
None
SDOUT2
32
O
D
SDOUT2 is one of the three serial data output ports. SDOUT2 supports four
discrete (stereo) data formats, and is capable of outputting data at bit rates up
to 24.576 MHz.
None
SDOUT3
33
O
D
SDOUT3 is one of the three serial data output ports. SDOUT3 supports four
discrete (stereo) data formats, and is capable of outputting data at bit rates up
to 24.576 MHz.
None
TEST
10
I
D
TEST is only used in factory tests. This pin must be left unconnected or
grounded.
Pulldown
相關(guān)PDF資料
PDF描述
TAS3103DBTR SPECIALTY CONSUMER CIRCUIT, PDSO38
TAS3103IDBTRG4 SPECIALTY CONSUMER CIRCUIT, PDSO38
TAS3103IDBTR SPECIALTY CONSUMER CIRCUIT, PDSO38
TAS3103IDCP SPECIALTY CONSUMER CIRCUIT, PDSO38
TAS3103DBTG4 SPECIALTY CONSUMER CIRCUIT, PDSO38
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TAS3103EVM 功能描述:音頻 DSP TAS3103 Eval Mod RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS3103IDBT 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS3103IDBTR 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS3103IDBTRG4 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS3108 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:AUDIO DIGITAL SIGNAL PROCESSORS