參數(shù)資料
型號(hào)： TAS3103DBTRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO38
封裝： GREEN, PLASTIC, TSSOP-38
文件頁數(shù)： 56/148頁
文件大?。?/td> 1247K
代理商： TAS3103DBTRG4
18
TERMINAL
PULLUP/
DOWN(2)
DESCRIPTION
NAME
PULLUP/
DOWN(2)
DESCRIPTION
TYPE(1)
I/O
NO.
VDDS (3.3 V)
31
-
PWR
VDDS is the 3.3-V pin that powers (1) the 1.8-V internal power regulator used
to supply logic power to the chip and (2) the I/O ring. It is recommended that
this pin be bypassed to DVSS (pin 28) with a low ESR capacitor in the range of
0.01
F.
None
XTALI (1.8-V logic)
4
I
A
XTALO and XTALI provide a master clock for the TAS3103 via use of an
external fundamental mode crystal. XTALI is the 1.8-V input port for the
oscillator circuit. See Note 3 for recommended crystal type and accompanying
circuitry. This pin should be grounded when the MCLKI pin is used as the
source for the master clock.
None
XTALO (1.8-V logic)
5
O
A
XTALO and XTALI provide a master clock for the TAS3103 via use of an
external fundamental mode crystal. XTALO is the 1.8-V output drive to the
crystal. XTALO can support crystal frequencies between 2.8 MHz and
20 MHz. See Note 3 for recommended crystal type and accompanying
circuitry. This pin should be left unconnected in applications using an external
clock input to MCLKI.
None
NOTES:
1. TYPE: A = analog; D = 3.3-V digital; PWR = power/ground/decoupling
2. All pullups are 20-
A weak pullups and all pulldowns are 20-A weak pulldowns. The pullups and pulldowns are included to assure
proper input logic levels if the pins are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive inputs
with pullups must be able to sink 20
A while maintaining a logic 0 drive level. Devices that drive inputs with pulldowns must be able
to source 20
A, while maintaining a logic 1 drive level.
3. Crystal type and recommended circuit:
OSC
Circuit
XO
XI
C1
C2
rd
AVSS
TAS3103
Crystal type = parallel-mode, fundamental-mode crystal
rd = drive level control resistor—vendor specified
CL = Crystal load capacitance (capacitance of circuitry between the two terminals of the crystal)
CL = (C1 × C2) / (C1 + C2) + CS (where CS = board stray capacitance ~2 pF)
Example: Vendor recommended CL = 18 pF, CS = 3 pF C1 = C2 = 2 x (18 3) = 30 pF
1.7
Operational Modes
The TAS3103 operation is governed by I/O terminal voltage level settings and register / coefficient settings within the
TAS3103. The terminal settings are wholly sufficient to address all external environments - allowing the remaining
configuration settings to be determined by either I2C commands or by the content of an I2C serial EEPROM (when
the I2C master mode is selected).
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