SLES197C – APRIL 2007 – REVISED MARCH 2011
www.ti.com
Power down of analog reference – The analog reference can be powered down if all DAC and ADC are
powered down. This operation is handled by the device controller through the ESFRs, and is made
available to the board controller via the I2C interface.
9.4
I
2C Bus Control (CS0)
The TAS3204 has a control to specify the slave and master I2C address. This control permits up to two
TAS3204 devices to be placed in a system without external logic. GPIO pins are level sensitive. They are
not edge triggered.
See
Section 8.3 for a complete description of this pin.
9.5
Programmable I/O (GPIO)
The TAS3204 has four GPIO pins and two general purpose input pins that are 8051 firmware
programmable.
GPIO1 and GPIO2 pins are single function I/O pins. Upon power up, GPIO1 is an input. If there is an
unsuccessful boot and GPIO1 is pulled high externally, the DAC output is disabled. If there is an
unsuccessful boot and the GPIO1 is pulled low externally, the DAC output is enabled. If there is a
successful boot, GPIO1 is pulled low by the internal MCU, and its function is defined by the boot code in
the EEPROM.
GPIO3 and GPIO4 pins are dual function I/O pins. These pins can be used as SDIN1 and SDIN2
respectively.
Mute and power down functions have to be programmed in the EEPROM boot code. These are
general-purpose input pins and can be programmed for functions other than mute and power down.
9.5.1
No EEPROM is Present or a Memory Error Occurs
Following reset or power-up initialization with the EEPROM not present or if a memory error occurs, the
TAS3204 is in one of two modes, depending on the setting of GPIO1.
GPIO1 is logic HIGH
With GPIO1 held HIGH during initialization, the TAS3204 comes up in the default configuration with the
serial data outputs not active. Once the TAS3204 has completed the default initialization procedure,
after the status register is updated and the I2C slave interface is enabled, then GPIO1 is an output and
is driven LOW. Following the HIGH-to-LOW transition of the GPIO pin, the system controller can
access the TAS3204 through the I2C interface and read the status register to determine the load
status.
If a memory-read error occurs, the TAS3204 reports the error in the status register (I2C subaddress
0x02).
GPIO1 is logic LOW
With GPIO1 held LOW during initialization, the TAS3204 comes up in an I/O test configuration. In this
case, once the TAS3204 completes its default test initialization procedure, the status register is
updated, the I2C slave interface is enabled, and the TAS3204 streams audio unaltered from input to
output as SDIN1 to SDOUT1, SDIN2 to SDOUT2, etc.
In this configuration, GPIO1 is an output signal that is driven LOW. If the external logic is no longer
driving GPIO1 low after the load has completed (~100 ms following a reset if no EEPROM is present),
the state of GPIO1 can be observed.
Then the system controller can access the TAS3204 through the I2C interface and read the status
register to determine the load status.
If the GPIO1 state is not observed, the only indication that the device has completed its initialization
procedure is the fact that the TAS3204 streams audio and the I2C slave interface has been enabled.
36
TAS3204 Control Pins
Copyright 2007–2011, Texas Instruments Incorporated