參數(shù)資料
型號(hào)： TAS3204PAG
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 41/76頁(yè)
文件大?。?/td> 1224K
代理商： TAS3204PAG
SLES197C – APRIL 2007 – REVISED MARCH 2011
www.ti.com
11.10 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I
2C-Bus
Devices
STANDARD
FAST
MODE
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
VIL
LOW-level input voltage
–0.5
0.8
–0.5
0.8
V
VIH
HIGH-level input voltage
2
V
Vhys
Hysteresis of inputs
N/A
0.05 VDD
V
LOW-level output voltage (open drain
VOL1
3-mA sink current
0
0.4
V
or open collector)
Bus capacitance from 10 pF
7 + 0.1 Cb
tof
Output fall time from VIHmin to VILmax
250
ns
to 400 pF
(1)
II
Input current, each I/O pin
–10
10
–10(2)
10(2)
μA
SCL pulse duration of spikes that must
tSP(SCL)
N/A
14(3)
ns
be suppressed by the input filter
SDA pulse duration of spikes that must
tSP(SDA)
N/A
22(3)
ns
be suppressed by the input filter
CI
Capacitance, each I/O pin
10
pF
(1)
Cb = capacitance of one bus line in pF. The output fall time is faster than the standard I
2C specification.
(2)
The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if VDD is switched off.
(3)
These values are valid at the 135-MHz DSP clock rate. If DSP clock is reduced by half, the tSP doubles.
11.11 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I
2C-Bus
Devices
all values are referred to VIHmin and VILmax (see Section 11.10)
STANDARD MODE
FAST MODE
PARAMETER
UNIT
MIN
MAX
MIN
MAX
fSCL
SCL clock frequency
0
100
0
400(1)
kHz
Hold time (repeated) START condition. After this period, the first
tHD-STA
4
0.6
μs
clock pulse is generated.
tLOW
LOW period of the SCL clock
4.7
1.3
μs
tHIGH
HIGH period of the SCL clock
4
0.6
μs
tSU-STA
Setup time for repeated START
4.7
0.6
μs
tSU-DAT
Data setup time
250
100
μs
tHD-DAT
Data hold time (2) (3)
0
3.45
0
0.9
μs
tr
Rise time of both SDA and SCL signals
1000
20 + 0.1 Cb
(4)
300
ns
tf
Fall time of both SDA and SCL
300
20 + 0.1 Cb
(4)
300
ns
tSU-STO
Setup time for STOP condition
4
0.6
μs
tBUF
Bus free time between a STOP and START condition
4.7
1.3
μs
Cb
Capacitive load for each bus line
400
pF
Noise margin at the LOW level for each connected device
VnL
0.1VDVDD
V
(including hysteresis)
Noise margin at the HIGH level for each connected device
VnH
0.2VDVDD
V
(including hysteresis)
(1)
In master mode, the maximum speed is 375 kHz.
(2)
Note that SDA does not have the standard I2C specification 300-ns internal hold time. SDA must be valid by the rising and falling edges
of SCL. TI recommends that a 2-k
pullup resistor be used to avoid potential timing issues.
(3)
A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU-DAT ≥ 250 ns must then be met.
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tr-max + tSU-DAT = 1000 + 250 = 1250 ns (according to the
standard-mode I2C bus specification) before the SCL line is released.
(4)
Cb = total capacitance of one bus line in pF
46
Electrical Specifications
Copyright 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TAS3204
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