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| 型號： | TAS3204PAG |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 64/76頁 |
| 文件大小： | 1224K |
| 代理商： | TAS3204PAG |
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www.ti.com
SLES197C – APRIL 2007 – REVISED MARCH 2011
Table 12-25. Extended Special Fucntion Registers (ESFR) (continued)
ESFR
MAPPED_TO
NO. OF
DIRECTION
CONNECTING
REGISTER TYPE
DESCRIPTION
BITS
BLOCK
1-bit asynchronous rstz
BD
Mode0_o
1
OUT
DSP
positive edge triggered
Reset low
Miscellaneous signal for MCU-DSP
communication.
1-bit asynchronous rstz
This is not a bit-addressable register, but
BE
Mode3_o
1
OUT
DSP
positive edge triggered,
contains bit data. The firmware must read in
Reset low
the data, mask the change, and write it back
out.
1-bit asynchronous rstz
BF
Mode4_o
1
OUT
DSP
positive edge triggered
Reset low
1-bit asynchronous rstz
C1
C1 Mode5_o
1
OUT
DSP
positive edge triggered
Reset low
1-bit asynchronous rstz
Miscellaneous signal for MCU-DSP
C2
Mode6_o
1
OUT
DSP
positive edge triggered
communication.
Reset low
This is not a bit-addressable register, but
contains bit data. The firmware must read in
1-bit asynchronous rstz
the data, mask the change, and write it back
C3
Mode7_o
1
OUT
DSP
positive edge triggered
out.
Reset low
1-bit asynchronous rstz
C4
Mode8_o
1
OUT
DSP
positive edge triggered
Reset low
1-bit asynchronous rstz
C5
GPIO_IN_t
1
IN
DSP
positive edge triggered
Registered input GPIO sense line
Reset Low
4-bit asynchronous rstz
GPIO bidirect configuration—low
→ output,
C6
gpio_enz_t
1
OUT
GPIO
positive edge triggered
high
→ input
Reset Low
1-bit asynchronous rstz
Drive value on GPIO line when configured
C7
gpio_out_t
1
OUT
GPIO
positive edge triggered
as output
Reset Low
1-bit asynchronous rstz
Reset-low sense lines for chip-select
C9
cs1
1
IN
CHIP_SEL
positive edge triggered
input/output
Reset Low
8-bit asynchronous rstz
CA
tb_loop_count_t
8
OUT
TONE
positive edge triggered
Tone slew rate counter configuration
Reset Low
CB
dlymemif_out
8
IN
DLY_MEM
NO REG – direct input
Low-byte delay interface date port
CC
dlymemif_out
8
IN
DLY_MEM
NO REG – direct input
High-byte delay interface date port
CD
dlymemif_out
8
IN
DLY_MEM
NO REG – direct input
High-byte delay interface date port
1-bit asynchronous rstz
CE
cntrl1_treb_active_t
1
OUT
TONE
positive edge triggered
Reset low
1-bit asynchronous rstz
CF
cntrl2_treb_active_t
1
OUT
TONE
positive edge triggered
Reset low
1-bit asynchronous rstz
Bit 0
cntrl3_treb_active_t
1
OUT
TONE
positive edge triggered
Reset low
Schedule tone coefficient calculations in the
audio DSP
1-bit asynchronous rstz
Bit 1
cntrl4_treb_active_t
1
OUT
TONE
positive edge triggered
Reset low
1-bit asynchronous rstz
Bit 2
cntrl1_bass_active_t
1
OUT
TONE
positive edge triggered
Reset low
1-bit asynchronous rstz
Bit 3
cntrl2_bass_active_t
1
OUT
TONE
positive edge triggered
Reset low
1-bit asynchronous rstz
Schedule tone coefficient calculations in the
Bit 4
cntrl3_bass_active_t
1
OUT
TONE
positive edge triggered
audio DSP
Reset low
1-bit asynchronous rstz
Schedule tone coefficient calculations in the
Bit 5
cnrtrl4_bass_active_t
1
OUT
TONE
positive edge triggered
audio DSP
Reset low
Copyright 2007–2011, Texas Instruments Incorporated
67
I2C Register Map
Product Folder Link(s): TAS3204
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