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參數(shù)資料
| 型號： | TB1261F |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA BiCMOS INTEGRATED CIRCUIT, SILICON MONOLITHIC |
| 中文描述： | 東芝的BiCMOS集成電路，硅單片 |
| 文件頁數(shù)： | 35/66頁 |
| 文件大?。?/td> | 1544K |
| 代理商： | TB1261F |
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TB1261F/TB1262F
2002-6-30 35 / 66
Note
P6
Items/Symbols
Video output S/N
/ S/N(p)
Bus conditions
RF AGC:except 0
PIF Freq. :
38.9MHz
Others : Preset
RF AGC:except 0
PIF Freq. :
38.9MHz
Others : Preset
Measurement methods
(1) Input a signal that 38.9[MHz], 90[dB( V)], and 87.5 [%]
modulated by black video signal at pin 6.
(2) Measure the video S/N for pin 68 output (HPF : 100[kHz],
LPF : 5[MHz], CCIR weighted) (S/N(p)[dB]).
(1) Input a signal composed of following 3 signals at pin 79;
38.90[MHz]/90[dB( V)],
34.47[MHz]/80dB( V)]
33.40[MHz]/80[dB( V)]
(2) Adjust pin 1 voltage so that the bottom of pin 68 output is
equal to sync. tip level.
(3) Measure the 1.07[MHz] level against the 4.43[MHz]
level(=0[dB]) (IM[dB]).
(1) Remove all connection from pin 79 and pin 80.
(2) Measure the resistance (Zin R(p)[k ]) and capacitance (Zin
C(p)[pF]) of pin 79 and pin 80 by the impedance meter.
P7
Intermodulation
/ IM
P8
PIF input resistance
/ Zin R(p)
PIF
capacitance
/ Zin C(p)
RF AGC output
voltage
/ VAGC max
/ VAGC min
input
Preset
P9
RF AGC:Adjust
PIF Freq. :
38.9MHz
Others : Preset
(1) Input a 38.9[MHz], 90[dB( V)] signal at pin 79.
(2) Adjust RF AGC so that the pin 78 voltage is 4.5V.
(3) Increase the IF input level to 107dB(uV).
(4) Measure the pin 78 voltage (VAGC min[V]).
(5) Connect pin 79 and pin 80 to GND.
(6) Measure the pin 78 voltage (VAGC max[V]).
P10
RF delay point
/ v Dly min
/ v Dly max
RF AGC
:
Adjust
PIF Freq.
38.9MHz
RF AGC: 01/3F
Others : Preset
(1) Input a 38.9[MHz], 90[dB( V)] signal at pin 79.
(2) Set the data of “RF AGC” to 01(h).
(3) Decrease the IF input level, measure the input level at
which the voltage at pin 78 turn to be 4.5[V] (v Dly
min[dB( V)]).
(4) Set the data of “RF AGC” to 3F(h).
(5) Increase the IF input level, measure the input level at
which the voltage at pin 78 turn to be 4.5[V] (v Dly
max[dB( V)]).
(1) Set the bit of “PIF Freq.” to “(0,1,1), 38.9MHz”.
(2) Input a signal that f0=38.9[MHz], 60[dB(V)] at pin 79.
(3) As read the bit of “IF lock”, sweep up/down the input signal
frequency.
(4) Measure fsuL, fsuH, fsdH, fsdL shown as below.
fpH(p) = fsdH – f0
fpL(p) = fsuL – f0
fhH(p) = fsuH – f0
fhL(p) = fsdL – f0
[Read BUS DATA] The bit of "IF lock"
IF LOCK 1
P11
Capture range of the
PLL
/ fpH(p)
/ fpL(p)
Hold range of the
PLL
/ fhH(p)
/ fhL(p)
RF AGC : except
0
PIF Freq. :
38.9MHz
Others : Preset
fhL(p)
fpH(p)
frequency
fpL(p)
fhH(p)
frequency
IF LOCK 0
IF LOCK 1
IF LOCK 0
(1) Set the bit of “VCO Adj. Req.” to “1”, and set the bit of “VCO
Adj. Req.” to “0”.
(2) Set the FET probe which connected to the spectrum analyzer
near by pin 50 or pin 51 (Don’t touch the probe directly to pin
50 or to pin 51).
(3) Apply 2.3[V] to pin 47, and measure frequency of the VCO
oscillation by the spectrum analyzer (fLVCO[MHz]).
(4) Apply 2.7[V] to pin 47, and measure frequency of the VCO
oscillation by the spectrum analyzer (fHVCO[MHz]).
(5) [MHz/V] = (fHVCO-fLVCO)/0.4
P12
Control steepness of
the VCO
/
PIF Freq. :
38.9MHz
Others : Preset
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