參數(shù)資料
型號(hào): TB1261F
廠商: Toshiba Corporation
英文描述: TOSHIBA BiCMOS INTEGRATED CIRCUIT, SILICON MONOLITHIC
中文描述: 東芝的BiCMOS集成電路,硅單片
文件頁數(shù): 40/66頁
文件大?。?/td> 1544K
代理商: TB1261F
TB1261F/TB1262F
2002-6-30 40 / 66
VIDEO stage (RGB Mute:0 / R cut off:128 / DC rest.:2(100%) / WPS:1(OFF))
Note
Items/Symbols
Bus conditions
V1
Y Input Dynamic
Range
/ DR
Y
Ydl=011(b)
Others: Preset
V2
Y Delay Time
/ t
YDELP
/ t
YDELS
/
Δ
t
YDEL-120
/
Δ
t
YDEL+160
/
Δ
t
YDEL step
Measurement methods
(1) Input a white signal with sync into Pin61.
(2) Increasing the Pin61 input amplitude, measure the
amplitude at which the Pin53 output is clipped, that is
"DR
Y
".
(1) Input a 2T pulse with sync and PAL burst into Pin61.
(2) Set the BUS data so that Y DL is 0ns(011).Observe the
Pin53 output, measure the delay time between Pin61 and
Pin53, that is "t
YDELP
".
(3) Set the BUS data so that Y DL is –120ns(000). Observe the
Pin53 output, measure the delay time between Pin61 and
Pin53 that is t
YDEL-120
.
(4) Set the BUS data so that Y DL is +160ns(111). Observe the
Pin53 output, measure the delay time between Pin61 and
Pin53 that is t
YDEL+160
.
(5) Calculate, “
Δ
t
YDEL-120
”= t
YDEL-120
- "t
YDEL
"
1.
Δ
t
YDEL+160
”= t
YDEL+160
- "t
YDEL
"
2.
Δ
t
YDEL
”= (“
Δ
t
YDEL+160
”- “
Δ
t
YDEL-120
”)/7
(6) Input a 2T pulse with sync and SECAM ID into Pin61.
(7) Set the BUS data so that Y DL is 0ns(011).Observe the
Pin53 output, measure the delay time between Pin61 and
Pin53, that is "t
YDELS
".
(1) Input a 0.5V(p-p), 4.43MHz signal with sync into Pin61.
(2) Measure the 4.43MHz amplitude at PIn53 for Chroma
Trap:1/0, that is V
TRAPON
/ V
TRAPOFF
.
(3) Calculate;"G
TRAP443
"=20*log(V
TRAPON
/V
TRAPOFF
)
(4) Input a 0.5V(p-p), 3.58MHz signal with sync into Pin61.
(5) Measure the 3.58MHz amplitude at PIn53 for Chroma
Trap:1/0, that is V
TRAPON
/ V
TRAPOFF
.
(6) Calculate;"G
TRAP358
"=20*log(V
TRAPON
/V
TRAPOFF
)
(1) Input 1Vp-p white signal with sync into pin #61
(2) Measure the gain between pin#61 and pin #53 for its
picture (without sync) level. Gy1
(1) Input a 0.5V(p-p) sweep signal with sync into Pin61.
(2) Measure the frequency at which the output amplitude is
3dB down against the level of 100Hz, which is "FR
Y
".
Y/Monout=0
ctrap = off
Y/Monout=0
ctrap = off
Ydl=parametric
Others: Preset
V3
Chroma Trap Gain
/ G
TRAP
Y/Monout=0
ctrap=parametric
Ydl=011(b)
Others: Preset
V4
Y gain
V5
Y Frequency
Response
/ FR
Y
Y/Monout=0
ctrap = off
Ydl=011(b)
Others: Preset
Y/Monout=1
videosw=paramet
ric
Others: Preset
V6
Mon out gain (MON)
(Y1/CVBS1) G
TV1
(Y2/CVBS2) G
TV2
(Y3/CVBS3) G
TV3
Y frequency response
FR
Y
(1) Input 1Vp-p white signal with sync into pin #61, #55, and
#44
(2) Measure the gain from pin#61, #55 and #44 to pin #53 in
switching the IICBUS of 'video sw'.
V7
Y/Mon out = 1
video sw = 00
Others: Preset
Y/Monout=1
videosw=paramet
ric
Others: Preset
(1) Input a 0.5V(p-p) sweep signal with sync into Pin61.
(2) Measure the frequency at which the output amplitude is
3dB down against the level of 100Hz, which is "FR
Y
".
(1) Input a sine wave signal (CVBS, V0=0.5Vp-p, f0=4MHz)
into pin 61, connect pin 55 and 44 to GND through 0.1F
capacitor.
(2) Set the bit of “Video SW” to “01, V2”, and measure the
amplitude of 4MHz signal at pin 53, that is V1-2.
(3) Set the bit of “Video SW” to “00, V1” and measure the
amplitude of 4MHz signal at pin 53, that is V1.
(4) “C CVBS1_2” = 20*log (V1-2 / V1)
(5) Measure the same way as (1)-(4) for others with the
combination of desired and undesired inputs,
V switch cross-talk
(CVBS1-CVBS2)
CT
CVBS1_2
(CVBS1-CVBS3)
CT
CVBS1_3
(CVBS2-CVBS1)
CT
CVBS2_1
(CVBS2-CVBS3)
CT
CVBS2_3
(CVBS3-CVBS1)
CT
CVBS3_1
(CVBS3-CVBS2)
CT
CVBS3_2
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