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參數(shù)資料
| 型號： | TC7109IJL |
| 廠商： | TelCom Semiconductor, Inc. |
| 英文描述： | 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS |
| 中文描述： | 12位向上兼容的模擬數(shù)字轉換器 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大小： | 274K |
| 代理商： | TC7109IJL |
3-100
TELCOM SEMICONDUCTOR, INC.
TC7109
TC7109A
12-BIT
μ
P-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
Figure 5. TC7109A RUN/HOLD Operation
The RUN/HOLD input may be used to shorten conver-
sion time. If RUN/HOLD goes LOW any time after zero
crossing in the deintegrate mode, the circuit will jump to
auto-zero and eliminate that portion of time normally spent
in deintegrate.
If RUN/HOLD stays or goes LOW, the conversion will
complete with minimum time in deintegrate. It will stay in
auto-zero for the minimum time and wait in auto-zero for a
HIGH at the RUN/HOLD input. As shown in Figure 5, the
STATUS output will go HIGH 7 clock periods after RUN/
HOLD is changed to HIGH, and the converter will begin the
integrate phase of the next conversion.
The RUN/HOLD input allows controlled conversion in-
terface. The converter may be held at idle in auto-zero with
RUN/HOLD LOW. The conversion is started when RUN/
HOLD goes HIGH, and the new data is valid when the
STATUS output goes LOW (or is transferred to the UART;
see "Handshake Mode"). RUN/HOLD may now go LOW,
terminating deintegrate and ensuring a minimum auto-zero
time before stopping to wait for the next conversion. Conver-
sion time can be minimized by ensuring RUN/HOLD goes
LOW during deintegrate, after zero crossing, and goes
HIGH after the hold point is reached. The required activity on
the RUN/HOLD input can be provided by connecting it to the
buffered oscillator output. In this mode, the input value
measured determines the conversion time.
Direct Mode
The data outputs (bits 1 through 8, low-order bytes; bits
9 through 12, polarity and overrange high-order bytes) are
accessible under control of the byte and chip enable termi-
nals as inputs with the MODE pin at a LOW level. These
three inputs are all active LOW. Internal pull-up resistors are
provided for an inactive HIGH level when left open. When
chip enable is LOW, a byte-enable input LOW will allow the
outputs of the byte to become active. A variety of parallel
data accessing techniques may be used, as shown in the
"Interfacing" section. (See Figure 6 and Table 1.)
The access of data should be synchronized with the
conversion cycle by monitoring the STATUS output. This
prevents accessing data while it is being updated and
eliminates the acquisition of erroneous data.
Symbol
Description
Min
Typ
Max
Units
t
BEA
t
DAB
Byte Enable Width
Data Access Time
From Byte Enable
Data Hold Time
From Byte Enable
Chip Enable Width
Data Access Time
From Chip Enable
Data Hold Time
From Chip Enable
200
500
150
nsec
nsec
300
t
DHB
150
300
nsec
t
CEA
t
DAC
300
500
200
nsec
nsec
400
t
DHC
200
400
nsec
Table 1. TC7109A Direct Mode Timing Requirements
Figure 6. TC7109A Direct Mode Output Timing
INTEGRATOR OUTPUT
INTERNAL CLOCK
DETERMINATED
AT ZERO CROSSING
DETECTION
AUTO-ZERO
PHASE I
MIN 1790 COUNTS
MAX 2041 COUNTS
STATIC IN
HOLD STATE
INT
PHASE II
RUN/HOLD input is ignored until end of auto-zero phase.
*
NOTE:
*
INTERNAL LATCH
STATUS OUTPUT
RUN/HOLD INPUT
7 COUNTS
= HIGH IMPEDANCE
CE/LOAD
AS INPUT
tCEA
tBEA
HBEN
AS INPUT
tDAB
tDAB
LBEN
AS INPUT
HIGH-BYTE
DATA
LOW-BYTE
DATA
DATA
tDAC
tDHC
DATA
VALID
DATA
VALID
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