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參數(shù)資料
| 型號： | TC7109IJL |
| 廠商： | TelCom Semiconductor, Inc. |
| 英文描述： | 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS |
| 中文描述： | 12位向上兼容的模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 274K |
| 代理商： | TC7109IJL |
3-99
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
INTERNAL CLOCK
INTEGRATOR OUTPUT
FOR NORMAL INPUT
INTEGRATOR
SATURATES
INTERNAL LATCH
INTEGRATOR OUTPUT
FOR OVERRANGE INPUT
NO ZERO
CROSSING
ZERO CROSSING
OCCURS
ZERO CROSSING
DETECTED
ZI
AZ
ZERO INTEGRATOR
PHASE FORCES
INTEGRATOR
OUTPUT TO 0V
INT
PHASE II
STATUS OUTPUT
AZ
PHASE I
DE
PHASE III
AZ
FIXED
2048
COUNTS
2048
COUNTS
MIN
4096
COUNTS
MAX
AFTER ZERO CROSSING, ANALOG SECTION
WILL BE IN AUTO-ZERO CONFIGURATION
NUMBER OF COUNTS TO ZERO CROSSING
PROPORTIONAL TO IN
TEST
17
POL
3
OR
4
B
12
5
B
11
6
B
10
7
B
9
8
B
8
9
B
7
10
B
6
11
B
5
12
B
4
13
B
3
14
2
26
22
23
24
25
21
STATUS
RUN/
HOLD
OSC
IN
OSC
OUT
OSC
SEL
BUFF
OSC
OUT
MODE
TO
ANALOG
SECTION
COMP OUT
AZ
INT
DE (
±
)
ZI
CONVERSION
CONTROL
LOGIC
OSCILLATOR
AND CLOCK
CIRCUITRY
HIGH-ORDER
BYTE OUTPUTS
LOW-ORDER
BYTE OUTPUTS
HANDSHAKE
LOGIC
B
2
15
B
1
16
27
SEND
18
19
20
LBEN
HBEN
CE/LOAD
1
GND
14 LATCHES
12-BIT COUNTER
14 THREE-STATE OUTPUTS
LATCH
CLOCK
Figure 4. Digital Section
Figure 3. Conversion Timing (RUN/HOLD Pin High)
TC7109
TC7109A
12-BIT
μ
P-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TC7109 | 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS |
| TC7109A | 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS |
| TC7109ACLW | 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS |
| TC7109ACPL | 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS |
| TC7109CLW | 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS |
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