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參數(shù)資料
| 型號： | TC7109IJL |
| 廠商： | TelCom Semiconductor, Inc. |
| 英文描述： | 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS |
| 中文描述： | 12位向上兼容的模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 274K |
| 代理商： | TC7109IJL |
3-103
TELCOM SEMICONDUCTOR, INC.
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Figure 9. TC7109A Handshake Triggered by MODE Input
DATA VALID
DATA VALID
TERMINATES
UART MODE
= HIGH IMPEDANCE
INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT
MODE INPUT
INTERNAL MODE
SEND INPUT
CE/LOAD AS OUTPUT
HBEN
HIGH-BYTE DATA
LBEN
LOW-BYTE DATA
= DON'T CARE
= WITH PULL-UP
UART
NORM
SEND
SENSED
SEND
SENSED
ZERO CROSSING DETECTED
ZERO CROSSING OCCURS
STATUS OUTPUT UNCHANGED
IN UART MODE
LATCH PULSE INHIBITED
IN UART MODE
POSITIVE TRANSITION
CAUSES ENTRY INTO
UART MODE
DE PHASE III
SEND
SENSED
Oscillator
The oscillator may be overdriven, or may be operated as
an RC or crystal oscillator. The OSCILLATOR SELECT
input optimizes the internal configuration of the oscillator for
RC or crystal operation. The OSCILLATOR SELECT input
is provided with a pull-up resistor. When the OSCILLATOR
SELECT input is HIGH or left open, the oscillator is config-
ured for RC operation. The internal clock will be the same
frequency and phase as the signal at the BUFFERED
OSCILLATOR OUTPUT. Connect the resistor and capaci-
tor as in Figure 10. The circuit will oscillate at a frequency
given by f = 0.45/RC. A 100 k
resistor is recommended for
useful ranges of frequency. The capacitor value should be
chosen such that 2048 clock periods are close to an integral
multiple of the 60 Hz period for optimum 60 Hz line rejection.
With OSCILLATOR SELECT input LOW, two on-chip
capacitors and a feedback device are added to the oscillator.
In this configuration, the oscillator will operate with most
crystals in the 1 to 5 MHz range with no external components
(Figure 11). The OSCILLATOR SELECT input LOW inserts
a fixed
4
58 divider circuit between the BUFFERED OSCIL-
LATOR OUTPUT and the internal clock. A 3.58 MHz TV
crystal gives a division ratio providing an integration time
given by:
t = (2048 clock periods) 58
The error is less than 1% from two 60 Hz periods, or
33.33 ms, which will give better than 40 dB, 60 Hz rejection.
The converter will operate reliably at conversion rates up
to 30 per second, corresponding to a clock frequency of
245.8 kHz.
When the oscillator is to be overdriven, the OSCILLA-
TOR OUTPUT should be left open, and the overdriving
signal should be applied at the OSCILLATOR INPUT. The
internal clock will be of the same duty cycle, frequency and
phase as the input signal. When the OSCILLATOR SELECT
is at GND, the clock will be 1/58 of the input frequency.
3.58 MHz
TC7109
TC7109A
12-BIT
μ
P-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
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| TC7109ACPL | 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS |
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