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參數(shù)資料
| 型號(hào)： | TDA9109A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 低費(fèi)用的I2C可控?fù)隙榷嗤斤@示器處理器 |
| 文件頁(yè)數(shù)： | 29/47頁(yè) |
| 文件大?。?/td> | 509K |
| 代理商： | TDA9109A |
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TDA9109A
29/47
Figure 5.
Figure 6.
The last featureperformed is the removal of equal-
ization pulses to avoid parasitic pulses on the
phase comparator (which would be disturbed by
missing or extraneous pulses). This last feature is
switched on/off by sub-address 0F D8. By default
[0], equalization pulses will not be removed.
2.2 PLL1
The PLL1 consists of a phase comparator, an ex-
ternal filter and a voltage-controlled oscillator
(VCO).The phase comparator is a “phase frequen-
cy” type designed in CMOS technology. This kind
Figure 7.
of phase detector avoids locking on wrong fre-
quencies. It is followed by a “charge pump”, com-
posed of two current sources : sunk and sourced
(typically I =1 mA when locked and I = 140
μ
A
when unlocked). This difference between lock/un-
lock allows smooth catching of the horizontal fre-
quency by PLL1. This effect is reinforced by an in-
ternal original slow down system when PLL1 is
locked, avoiding the horizontal frequency chang-
ing too quickly. The dynamic behavior of PLL1 is
fixed by an external filter which integrates the cur-
rent of the charge pump. A “CRC” filter is generally
used (see Figure 7)
7
4.7
μ
F
PLL1F
10nF
1.8k
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