參數(shù)資料
型號: TDA9109A
廠商: 意法半導(dǎo)體
英文描述: LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
中文描述: 低費用的I2C可控撓度多同步顯示器處理器
文件頁數(shù): 34/47頁
文件大?。?/td> 509K
代理商: TDA9109A
TDA9109A
34/47
3 VERTICAL PART
3.1 Function
When the synchronization pulse is not present, an
internal current source sets the free running fre-
quency. For an external capacitor, C
OSC
= 150nF,
the typical free running frequency is 100Hz.
The typical free running frequency can be calculat-
ed by:
fo(Hz) = 1.5
.
10
-5 .
C
OSC
A negative or positive TTL level pulse applied on
Pin 2 (VSYNC) as well as a TTL composite sync
on Pin 1 can synchronize the ramp in the range
[fmin, fmax] (See Figure 16). This frequency range
depends on the external capacitor connected on
Pin 22.A 150nF (
±
5%) capacitoris recommended
for 50Hz to 185Hz applications.
If a synchronization pulse is applied, the internal
oscillator is synchronized immediately but with
wrong amplitude. An internal correction then ad-
justs it in less than half a second. The top value of
the ramp (Pin 22) is sampled on the AGC capaci-
tor (Pin 20) at each clock pulse and a transcon-
ductance amplifier modifies the charge current of
the capacitor in such a way to make the amplitude
constant again.
The readstatus register provides the vertical Lock-
Unlock and the vertical sync polarity information.
We recommend the use of an AGC capacitor with
low leakage current. A value lower than 100nA is
mandatory.
A good stability of the internal closed loop is
reached by a 470nF
±
5% capacitor value on Pin
20 (VAGC).
3.2 I
2
C Control Adjustments
S and C correction shapes can then be added to
this ramp. These frequency-independent S and C
corrections are generated internally. Their ampli-
tudes are adjustable by their respective I
2
C regis-
ters. They can also be inhibited by their ”select”
bits.
Finally, the amplitude of this S and C corrected
ramp can be adjusted by the vertical ramp ampli-
tude control register.
The adjusted ramp is available on Pin 23 (V
OUT
) to
drive an external power stage.
The gain of this stage can be adjusted (
±
25%) de-
pending on its register value.
The mean value of this ramp is driven by its own
I
2
C register (vertical position). Its value is
VPOS = 7/16
.
V
REF-V
±
400mV.
Usually V
OUT
is sent through a resistive divider to
the inverting input of the booster. Since VPOS de-
rives fromV
REF-V
,the biasvoltage sent to thenon-
inverting input of the booster should also derive
from V
REF-V
to optimize the accuracy (see Appli-
cation Diagram).
3.3 Vertical Moiré
By using the verticalmoiré, VPOS canbe modulat-
ed from frame to frame. This function is intended
to cancel the fringes which appearwhen the line to
line interval is very close to the CRT vertical pitch.
The amplitude of the modulation is controlled by
register VMOIRE on sub-address 0C and can be
switched-off via the control bit D8.
1
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