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參數(shù)資料
| 型號： | TDA9109A |
| 廠商： | 意法半導體 |
| 英文描述： | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 低費用的I2C可控撓度多同步顯示器處理器 |
| 文件頁數(shù)： | 31/47頁 |
| 文件大小： | 509K |
| 代理商： | TDA9109A |
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TDA9109A
31/47
The TDA9109A also includes a Lock/Unlock iden-
tification block which senses in real time whether
PLL1 is locked or not on the incoming horizontal
sync signal.
The lock/unlock information is available through
the I
2
C read and the pin 3 voltagelevel
PLL1 Timing Diagram
Figure 10.
2.3 PLL2
PLL2 ensures a constant position of the shaped
flyback signal in comparison with the sawtooth of
the VCO, taking into account the saturation time
Ts (see Figure 11)
Figure 11. PLL2 Timing Diagram
The phase comparator of PLL2 (phase type com-
parator) is followed by a charge pump (typical out-
put current: 0.5 mA).
The flyback input consists of an NPN transistor.
This input must be current driven. The maximum
recommended
input
(see Figure 12).
Figure 12. Flyback Input Electrical Diagram
current
is
5 mA
The dutycycle is adjustable through I
2
C from30 %
to 65 %. For a safe start-up operation, the initial
duty cycle (after power-on reset) is 65% in order to
avoid having too long a conduction period of the
horizontal scanning transistor.
The maximum storage time (Ts Max.) is (0.44T
H
-
T
FLY
/2). Typically, T
FLY
/T
H
is around 20 % which
means that Ts max is around 34 % of T
H
.
The PLL1 ensures the exact coincidence between the
signal phase REF and HSYNC. A
±
10% T
phase
adjustment is possible around the 3.4V point.
Phase REF1 is obtained by comparison between
the sawtooth and a DC voltage adjustable between
2.9 V and 4.2 V.
H O
Sawtooth
7/8 T
H
1/8 T
H
6.4V
Ref. for H Position
Vb
(2.9V<Vb<4.2V)
1.6V
REF1
HSync
HOsc
Sawtooth
7/8T
H
1/8 T
H
Flyback
Internally
shaped Flyback
HDrive
Ts
Duty Cycle
1.6V
4.0V
6.4V
500
HFly
12
Q1
GND 0V
20k
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| TDA9109N | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
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