參數(shù)資料
型號(hào)： THS8083APZP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： GREEN, PLASTIC, HTQFP-100
文件頁(yè)數(shù)： 11/63頁(yè)
文件大小： 320K
代理商： THS8083APZP
36
The PFD produces a digital error value, signaling the phase/frequency difference between the HS input and the
divided PLL output clock. The integrated digital PLL loop filter subsequently filters this error value. This filter consists
of proportional and integrator (accumulator) parts. Gains of both parts are programmable (GAIN_N and GAIN_P
register values), each with eight settings. The higher the programmed value, the higher the gain in either the
proportional or integrator portions of the filter, which translates into a wider capture range and faster acquisition but
also into higher steady-state jitter.
The PFD also provides a LOCK output on a dedicated terminal. This output has programmable hysteresis
(LD_THRES register value). Details are explained in the Register Description section. The LOCK output is made
available on a dedicated pin so that the user could implement additional functionality before using this output (e.g.,
implement the sticky nature of an unlock condition by routing it through an external set/reset flip-flop).
By integrating the loop filter and making it programmable, the user can trade off both at runtime depending on the
quality of the incoming HS signal (inaccurate frequency, jitter content).
The filtered phase/frequency error value is now used to correct the programmed nominal DTO increment (NOM_INC
register value). This updated DTO increment (DTO_INC register value) is used by the DTO and determines the
instantaneous DTO output frequency. By making DTO_INC available as a read-only register, the user can read out
via I2C and calculate the instantaneous frequency of the DTO-generated clock.
Because of the digital nature of the PLL, the loop can be opened while still keeping an accurate frequency output.
Therefore, the PLL can also be used as a frequency synthesizer without any HS reference. This is done by disabling
the PFD (PFD_DISABLE register value). This keeps DTO_INC always equal to NOM_INC, thereby producing a DTO
output frequency always equal to the desired programmed frequency, irrespective of HS.
There is a second option to operate in open loop. In some video/graphics modes, no valid HS is present during a part
of the frame/field period, typically during some lines of the VBI (vertical blanking interval). In order to have an accurate
PLL output clock and avoid clock drift, the PFD output needs to be held constant during this time. The PFD FREEZE
pin provides this option. Asserting this pin freezes DTO_INC to its present value, thereby producing a constant PLL
output clock frequency, not necessarily equal to the nominal desired frequency programmed by NOM_INC. Together
with the composite sync slicer, this feature allows using the PLL with input signals containing embedded composite
sync with minimal external logic. See the Composite Sync Slicer section.
The phase of the PLL generated clock can be programmed in 31 uniform steps over a single clock period
(360/31 = 11.6 degrees phase resolution) so that the sampling phase of the ADC can be accurately controlled.
In addition to sourcing the ADC channel clock from the PLL, an external pixel clock can be used (from terminal
EXT_ADCCLK). If configured this way (via SEL_ADCCLK register value), a clock signal of the required sampling
frequency should be applied to EXT_ADCCLK; this signal, instead of the PLL generated clock, is routed to the ADC
channels. In this case no phase control is available on the external clock signal. Still, the internal PLL can be used
and its output made available externally as explained below. This means two clock domains can be implemented on
the THS8083A: one is externally fed, and the other, possibly asynchronous to the first, generated by the internal PLL.
This provides considerable flexibility in the design of video/graphics equipment that implements scaling and frame
rate conversion.
相關(guān)PDF資料
PDF描述
THS8083APZPG4 SPECIALTY CONSUMER CIRCUIT, PQFP100
THS8083CPZP SPECIALTY CONSUMER CIRCUIT, PQFP100
THS8133ACPHP PARALLEL, WORD INPUT LOADING, 0.005 us SETTLING TIME, 10-BIT DAC, PQFP48
THS8133BCPHP PARALLEL, WORD INPUT LOADING, 0.005 us SETTLING TIME, 10-BIT DAC, PQFP48
THS8133BCPHPG4 PARALLEL, WORD INPUT LOADING, 0.005 us SETTLING TIME, 10-BIT DAC, PQFP48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
THS8083APZP 制造商:Texas Instruments 功能描述:8BIT ADC 80MSPS TRIPLE SMD 8083
THS8083APZPG4 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Tr 8B 95MSPS 3.3V Vid & Graphics Dig RoHS:否 制造商:Texas Instruments 輸入信號(hào)類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel
THS8083CPZP 制造商:Rochester Electronics LLC 功能描述:- Bulk
THS8083EVM 制造商:Texas Instruments 功能描述:THS8083EVM - Bulk
THS8083T 制造商:TI 制造商全稱:Texas Instruments 功能描述:Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*