參數(shù)資料
型號(hào): THS8083APZP
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: GREEN, PLASTIC, HTQFP-100
文件頁數(shù): 17/63頁
文件大小: 320K
代理商: THS8083APZP
311
3.11 Register Description
Register values after reset/at power up/after power down mode: The default value with each register shows the
start-up condition after general chip reset. The register state after power up is undefined i.e., the device requires a
reset after power up (RESET low) to put all registers in their default states. The value of these registers is preserved
in all power-down modes (i.e. after power down the register values are identical as when entering power down); they
do not return to their default values under this condition. In order for the device to reset correctly, a master clock signal
needs to be applied during reset from either a clock signal on XTL1MCLK or a crystal connected between
XTL1MCLK and XTL2. The reset signal needs to be at least 5 clock cycles wide.
Default values: The default values for this device are set for XGA@78.75 MHz.
3.11.1 Register Name: TERM_CNT_0
Subaddress: 00 (R/W)
TERM_CNT7
TERM_CNT6
TERM_CNT5
TERM_CNT4
TERM_CNT3
TERM_CNT2
TERM_CNT1
TERM_CNT0
MSB
LSB
TERM_CNT[7..0]:
TERM_CNT[11..0] sets the number of pixels per line. Controls the digital PLL feedback divider.
Default: 0x20
3.11.2 Register Name: TERM_CNT_1
Subaddress: 01 (R/W)
X
TERM_CNT11
TERM_CNT10
TERM_CNT9
TERM_CNT8
MSB
LSB
TERM_CNT[11..8]:
See register TERM_CNT_0.
Default: 0x5
Default TERM_CNT: 0x520 = 1312 pixels/line (XGA@75 Hz)
3.11.3 Register Name: NOM_INC_0
Subaddress: 02 (R/W)
NOM_INC7
NOM_INC6
NOM_INC5
NOM_INC4
NOM_INC3
NOM_INC2
NOM_INC1
NOM_INC0
MSB
LSB
NOM_INC[7..0]:
NOM_INC[32..27]: integer part of DTO increment value
NOM_INC[26..0] : fractional part of DTO increment value
(See Appendix A for how to calculate the increment)
Default: 0x16
3.11.4 Register Name: NOM_INC_1
Subaddress: 03 (R/W)
NOM_INC15
NOM_INC14
NOM_INC13
NOM_INC12
NOM_INC11
NOM_INC10
NOM_INC9
NOM_INC8
MSB
LSB
NOM_INC[15..8]:
See register NOM_INC_0.
Default: 0x8A
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