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參數(shù)資料
| 型號： | THS8083APZP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 14/63頁 |
| 文件大?。?/td> | 320K |
| 代理商： | THS8083APZP |
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38
3.7
Output Formatter
This block enables either a 4:4:4 24-bit output or a 4:4:4 48-bit output at half the pixel clock, or a 4:2:2 16-bit output
useful for YUV digitizing (ITU.BT-601 style). In the latter case, an 8-bit port is used for the Y output while a second
8-bit port is used alternately for Cr or Cb. As per ITU BT-601, Cb is the first video data word for each line, as shown
in Figure 2-7.
The first color sample after an incoming HS is Cb. The output signal DHS is synchronized to the first pixel of a line
and can therefore be used to uniquely identify Cb from Cr output data in down-sampled modes.
Cb
Cr
Cb
Cr
Cb
YY
Y
2 Channels
3 Channels
Cr (R-Y or V)
Cb (or B-Y or U)
Sampling Format
Y
X
Y
On Ch1 Bus A
Output
On Ch2 Bus A
Output
Other Outputs HI-Z
Output Format
t
Output Formatter Combines Ob
and Cr On Single Output Bus
Figure 37. Output Formatter
3.8
Power Down
Three power down modes are defined in the I2C power-down register, :
Chip power down: PWDN_ALL
When PWDN_ALL=1, all analog circuits are powered down except the internal bandgap reference, the
circuit that generates the clamping voltages and the sync reference voltage. All these are kept active for
the composite sync slicer that remains active during power down. The clock frequency of the digital circuitry
is lowered to reduce power consumption when in power down.
Internal reference power down: PWDN_REF
When PWDN_REF=1, bottom and top references (VREFB, VREFT) on all channels become inputs and
should be externally driven.
Bandgap reference power down: PWDN_BGAP
When PWDN_BGAP=1, the internal bandgap reference voltage is inactive and terminal VMID should be
externally driven.
Additionally, the DTO circuitry can be disabled:
DTO power down: DTO_DIS
When DTO_DIS=1, the DTO frequency is lowered to reduce power dissipation. This feature can be
activated when an external sampling clock is used (EXT_ADCCLK).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THS8083APZP | 制造商:Texas Instruments 功能描述:8BIT ADC 80MSPS TRIPLE SMD 8083 |
| THS8083APZPG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Tr 8B 95MSPS 3.3V Vid & Graphics Dig RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| THS8083CPZP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| THS8083EVM | 制造商:Texas Instruments 功能描述:THS8083EVM - Bulk |
| THS8083T | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL |
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