參數(shù)資料
型號(hào)： THS8083CPZP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： POWER, THERMALLY ENHANCED, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 43/61頁(yè)
文件大?。?/td> 266K
代理商： THS8083CPZP
5–4
5.4.4
I2C Interface
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIL
Low-level input voltage
0.99
V
VIH
High-level input voltage
2.31
V
f(SCL)
SCL clock frequency
0
400/100
kHz
t(LOW)
Low period of SCL
Valid for I2C fast mode support only.
1.3
s
t(HIGH)
High period of SCL
Valid for I2C fast mode su
ort only.
See footnotes to SCL clock frequency.
0.6
s
th(DATA)
Data hold time
0§
s
tsu(DATA)
Data setup time
100
s
C(b)
Capacitive load for each bus line#
400
pF
For DTO clock frequencies of minimum 25 MHz (I2C fast mode)
For DTO clock frequencies of below 25 MHz (I2C normal mode)
§ The device must internally provide a hold time of 300 ns for the SDA signal (referred to VIH(min) of the SCL signal) in order to bridge the undefined
region of the falling edge of SCL.
If the device is used in a standard mode I2C system the requirement of tsu(DATA)>=250 ns must be met.
# Cb= total capacitance of one bus line in pF
5.4.5
ADC Channel
5.4.5.1 DC Accuracy
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Integral nonlinearity (INL)
PLL (see Note 7)
25
±125
25
LSB
Integral nonlinearity (INL)
PLL (see Note 7)
–2.5
±1.25
2.5
LSB
Differential nonlinearity (DNL)
PLL (see Note 8)
1
0 6/1
175
LSB
Differential nonlinearity (DNL)
PLL (see Note 8)
–1
–0.6/1
1.75
LSB
No missing codes
Assured
Gain error
ADC_INTREF (see Note 9)
20
mV
Offset error
ADC_INTREF (see Note 10)
–20
mV
Assured at nominal voltage supply levels only.
NOTES:
7. Integral nonlinearity (INL) – Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full
scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond
the last code transition. The deviation is measured from the center of each particular code to the true straight line between these
two endpoints.
8. Differential nonlinearity (DNL) – An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this
ideal value. Therefore, this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here
as the step size for the device under test (i.e., last transition level – first transition level)/(2n – 2). Using this definition for DNL
separates the effects of gain and offset error. A DNL of less than
±1 LSB ensures no missing codes. A DNL of less than ±1/2 LSB
assures monotonic behavior.
9. Gain error – The first code transition should occur for an analog value 1/2 LSB above nominal negative full scale (the voltage applied
to the REFBI terminal). The last transition should occur for an analog value 1/2 LSB below nominal positive full scale (the voltage
applied to the REFTI terminal). Gain error is defined here as the deviation from the ideal location of the highest transition level on
the ADC transfer function.
10. Offset error – The first code transition should occur at a level 1/2 LSB above zero. Offset is defined as the deviation of the actual
first code transition from that point.
5.4.5.2 Dynamic Performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PARAMETER
ADC_INTREF
MIN
TYP
MAX
UNIT
Effective number of bits, ENOB
fI = 20 MHz
6.4
Bits
Signal-to-total ratio without distortion, SNR
fI = 20 MHz
40.5
dB
Total harmonic distortion, THD
fI = 1 MHz
–43.5
dB
Spurious free dynamic range, SFDR
fI = 1 MHz
49
dB
Analog input full-power bandwidth, BW
(see Note 11)
500
MHz
Based on analog input voltage of 1 dB FS referenced to the full-scale input range and a clock signal with 50% duty cycle.
相關(guān)PDF資料
PDF描述
THS8133ACPHP PARALLEL, WORD INPUT LOADING, 0.005 us SETTLING TIME, 10-BIT DAC, PQFP48
THS8133BCPHP PARALLEL, WORD INPUT LOADING, 0.005 us SETTLING TIME, 10-BIT DAC, PQFP48
THS8133BCPHPG4 PARALLEL, WORD INPUT LOADING, 0.005 us SETTLING TIME, 10-BIT DAC, PQFP48
THS8133CPHP PARALLEL, WORD INPUT LOADING, 0.005 us SETTLING TIME, 10-BIT DAC, PQFP48
THS8134BCPHP PARALLEL, 8 BITS INPUT LOADING, 0.005 us SETTLING TIME, 8-BIT DAC, PQFP48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
THS8083EVM 制造商:Texas Instruments 功能描述:THS8083EVM - Bulk
THS8083T 制造商:TI 制造商全稱:Texas Instruments 功能描述:Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL
THS8-10R-D 制造商:Thomas & Betts 功能描述:CATAMOUNT CABLE TIES
THS8133 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION WITH TRI-LEVEL SYNC GENERATION
THS8133_07 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION WITH TRI-LEVEL SYNC GENERATION
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*