參數(shù)資料
型號： TLIU04C1
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface(四T1/E1線接口)
中文描述： 四T1/E1線路接口（四個(gè)T1/E1線接口）
文件頁數(shù)： 29/100頁
文件大?。?/td> 1321K
代理商： TLIU04C1
Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
29
Lucent Technologies Inc.
Microprocessor Mode
(continued)
Output Pulse Generation
The transmitter accepts a clock with NRZ data in
single-rail mode (DUAL = 0: register 5, bit 4) or a clock
with positive and negative NRZ data in dual-rail mode
(DUAL = 1) from the system. The device converts this
data to a balanced bipolar signal (AMI format) with
optional B8ZS(DS1)/HDB3(CEPT) encoding and jitter
attenuation. Low-impedance output drivers produce
these pulses on the line interface. Positive ones are
output as a positive pulse on TTIP and negative ones
are output as a positive pulse on TRING. Binary zeros
are converted to null pulses. The total delay of the data
from the system interface to the transmit driver is
approximately 3 to 11 bit periods, depending on the
code configuration (see the Zero Substitution Decoding
(CODE) section, page 20 and the Zero Substitution
Encoding (CODE) section, page 30).
Additional delay results if the jitter attenuator is
selected for use in the transmit path (see the LIU Delay
Values section).
Transmit pulse shaping is controlled by the on-chip
pulse-width controller and pulse equalizer. The pulse-
width controller produces high-speed timing signals to
accurately control the transmit pulse widths. This elimi-
nates the need for a tightly controlled transmit clock
duty cycle that is usually required in discrete imple-
mentations. The pulse equalizer controls the ampli-
tudes of the pulses. Different pulse equalizations are
selected through proper settings of EQA, EQB, and
EQC (registers 6—9, bits 5—7) as described in
Table 12.
Table 12. Equalizer/Rate Control
* In DS1 mode, the distance to the DSX for 22 gauge PIC (ABAM) cable is specified. Use the maximum cable loss figures for other cable types.
In CEPT mode, equalization is specified for coaxial or twisted-pair cable.
Loss measured at 772 kHz.
In 75
applications, Option 1 is recommended over Option 2 for lower device power dissipation. Option 2 allows for the same transformer as
used in CEPT 120
applications.
Jitter
The intrinsic jitter of the transmit path, i.e., the jitter at TTIP/TRING when no jitter is applied to TCLK (and the jitter
attenuator is not selected, JAT = 0), is typically 5 nsp-p and will not exceed 0.02 UIp-p.
EQA
EQB
EQC
Service
Clock
Rate
Transmitter Equalization
*
Maximum
Cable Loss
Feet
Meters
dB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DS1
1.544 MHz
0 ft. to 131 ft.
131 ft. to 262 ft.
262 ft. to 393 ft.
393 ft. to 524 ft.
524 ft. to 655 ft.
0 m to 40 m
40 m to 80 m
80 m to 120 m
120 m to 160 m
160 m to 200 m
0.6
1.2
1.8
2.4
3.0
—
—
—
CEPT
2.048 MHz
75
(Option 2)
120
or 75
(Option 1)
—
Not Used
—
相關(guān)PDF資料
PDF描述
TLV3011AIDBVR Nanopower, 1.8V, SOT23 Comparator with Voltage Reference
TLV349x CAPACITOR, CLASS Y2 1.0NFCAPACITOR, CLASS Y2 1.0NF; Capacitance:1nF; Voltage rating, AC:250V; Voltage rating, DC:2500V; Capacitor dielectric type:Polypropylene; Series:B81122; Tolerance, +:20%; Tolerance, -:20%; Temp, op.
TLV3011AIDBVT Nanopower, 1.8V, SOT23 Comparator with Voltage Reference
TLV3011AIDCKR Nanopower, 1.8V, SOT23 Comparator with Voltage Reference
TLV3011AIDCKT Nanopower, 1.8V, SOT23 Comparator with Voltage Reference
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLIXF30001 制造商:GIGA 功能描述:
TLIXF30003 制造商:Rochester Electronics LLC 功能描述:- Bulk
TLIXF30007-852838 制造商:Cortina Systems Inc 功能描述:
TLIXF30009-865852 功能描述:IC OPT TRANSPORT PROC 868-TBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:*
TLIXF30010 制造商:Intel 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*