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參數(shù)資料
| 型號： | TLIU04C1 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface(四T1/E1線接口) |
| 中文描述： | 四T1/E1線路接口（四個T1/E1線接口） |
| 文件頁數(shù)： | 65/100頁 |
| 文件大?。?/td> | 1321K |
| 代理商： | TLIU04C1 |
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Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
65
Lucent Technologies Inc.
Direct Logic Control Mode
(continued)
Pin Information
(continued)
Table 39. Pin Descriptions
(continued)
* I = input, O = output, I
u
indicates an input with internal pull-up; I
d
indicates an input with internal pull-down, P = power. Resistance value of all
internal pull-ups or pull-downs is 50 k
, unless otherwise specified.
Pin
Symbol
Type
*
I
d
Qty
Name/Description
111
JAT
1
Jitter Attenuator in the Transmit Path.
Setting JAT = 1 enables
the jitter attenuator in the transmit path for all four channels. Setting
JAT = 0 disables the jitter attenuator in the transmit path. If both
JAT = 1 and JAR = 1, the jitter attenuator is disabled.
Jitter Attenuator in the Receive Path.
Setting JAR = 1 enables
the jitter attenuator in the receive path for all four channels. Setting
JAR = 0 disables the jitter attenuator in the receive path. If both
JAT = 1 and JAR = 1, the jitter attenuator is disabled.
Chip Mode.
This pin sets the chip mode for either direct logic mode
or microprocessor mode.
Microprocessor:CMODE = 1
Direct Logic:
CMODE = 0
Jitter Attenuator Bandwidth Adjust.
Setting this pin selects the
lower bandwidth jitter attenuator option in CEPT mode, lowering the
bandwidth from 10 Hz to 1.25 Hz. When this option is used, XCLK
must be ±20 ppm. See Table 54.
Alternate Logic Mode (ALM).
If ALM = 0, the receiver circuitry
(and transmit input) assumes the data to be active-low polarity. If
ALM = 1, the data is assumed to be active-high polarity.
Alternate Clock Mode (ACM).
The alternate clock mode control
pin selects the positive or negative clock edge of the receive clock
(RCLK) for receiver data retiming. For ACM = 1, the receive data is
retimed on the positive edge of the receive clock. When ACM = 0,
the receive data is retimed on the negative edge of the receive
clock. (This does not affect transmit clock timing.) See Figure 38.
Dual-Rail Mode Select.
This pin is cleared (DUAL = 0) for single-
rail mode and set (DUAL = 1) for dual-rail mode.
Hardware Reset (Active-Low).
If RESET is forced low, all internal
states in the transceiver paths are reset and data flow through each
channel will be momentarily disrupted. The RESET pin must be
held low for a minimum of 1 ms.
High-Impedance Mode (Active-Low).
When ICT = 0, all output
buffers (TTIP TRING, RCLK, RPD, RND, LOXC, LOTC, TDM,
DLOS, ALOS) are placed in a high-impedance state. TTIP and
TRING outputs have a limited high-impedance capability of
approximately 8 k
.
Power Supply for Digital Circuitry.
110
JAR
I
d
1
118
CMODE
I
d
1
38
JABW0
I
d
1
114
ALM
I
d
1
115
ACM
I
d
1
112
DUAL
I
d
1
44
RESET
I
u
1
43
ICT
I
u
1
2, 11, 47,
74, 83,
119
1, 12, 37,
48, 73, 84,
109, 120
113
V
DDD
P
6
GND
D
P
8
Ground Reference for Digital Circuitry.
NC
—
1
No Connect.
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