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參數(shù)資料
| 型號： | TLIU04C1 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface(四T1/E1線接口) |
| 中文描述： | 四T1/E1線路接口（四個T1/E1線接口） |
| 文件頁數(shù)： | 42/100頁 |
| 文件大?。?/td> | 1321K |
| 代理商： | TLIU04C1 |
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Advance Data Sheet, Rev. 2
TLIU04C1 Quad T1/E1 Line Interface
April 1999
42
Lucent Technologies Inc.
Microprocessor Mode
(continued)
Powerdown (PWRDN)
Each line interface channel has an independent power-
down mode controlled by PWRDN (registers 6—9,
bit 0). This provides power savings for systems that use
backup channels. If PWRDN = 1, the corresponding
channel will be in a standby mode, consuming only a
small amount of power. It is recommended that the
alarm registers for the corresponding channel be
masked with MASK = 1 (registers 6—9, bit 1) during
powerdown mode. If a line interface channel in power-
down mode needs to be placed into service, the chan-
nel should be turned on (PWRDN = 0) approximately
5 ms before data is applied.
Reset (RESET, SWRESET)
The device provides both a hardware reset (
RESET
;
pin 44) and a software reset (SWRESET; register 4,
bit 1) that are functionally equivalent. INT (pin 114) is
also cleared. The writable microprocessor interface
registers are not affected by reset, with the exception of
bits in register 4 (see the Global Control Registers
(0100, 0101) section). During a reset condition, data
transmission will be interrupted.
The reset condition is initiated by setting
RESET
= 0 or
SWRESET = 1 for a minimum of 10 μs. After releasing
the reset control (RESET = 1 or SWRESET = 0), the
device will stay in the reset condition for approximately
2.7 ms to ensure stabilization of the PLL. After leaving
the reset condition (with
RESET
= 1 or SWRESET = 0),
the bits in register 4 will be reset and may need to be
restored.
Loss of XCLK Reference Clock (LOXC)
The LOXC output (pin 45) is active when the XCLK ref-
erence clock (pin 46) is absent. The LOXC flag is
asserted a maximum of 16 μs after XCLK disappears,
and deasserts immediately after detecting the first
clock edge of XCLK.
During the LOXC alarm condition, the clock recovery
and jitter attenuator functions are automatically dis-
abled. Therefore, if CDR = 1 and/or JAR = 1, the RCLK,
RPD, RND, and DLOS outputs will be unknown. If CDR
= 0, there will be no effect on the receiver. If the jitter
attenuator is enabled in the transmit path (JAT = 1) dur-
ing this alarm condition, then a Loss of Transmit Clock
alarm, LOTC = 1, will also be indicated.
In-Circuit Testing and Driver High-Imped-
ance State (
ICT
)
The function of the
ICT
input (pin 43) is determined by
the ICTMODE bit (register 4, bit 3). If ICTMODE = 0
and
ICT
is activated (
ICT
= 0), then all output buffers
(TTIP TRING, RCLK, RPD, RND, LOXC, RDY_
DTACK
,
INT, AD[7:0]) are placed in a high-impedance state. For
in-circuit testing, the
RESET
pin can be used to activate
ICTMODE = 0 without having to write the bit. If
ICTMODE = 1 and
ICT
= 0, then only the TTIP and
TRING outputs of all channels will be placed in a high-
impedance state. The TTIP and TRING outputs have a
limiting high-impedance capability of approximately
8 k
.
LIU Delay Values
The transmit coder has 5 UI delay whether it is in the
path or not and whether it is B8ZS or HDB3. Its delay is
only removed when in single-rail mode. The remainder
of the transmit path has 4.6 UI delay. The receive
decoder has 5 UI delay whether it is in the path or not
and whether it is B8ZS or HDB3. Its delay is only
removed when in single-rail mode or CDR = 0. The
AFE (equalizer plus slicer) delay is nearly 0 UI delay.
The jitter attenuator delay is nominally 33 UI but can be
2 UI—64 UI depending on the state. The DPLL used for
timing recovery has 8 UI delay.
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