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參數(shù)資料
| 型號： | TLV2548MPWREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 10/37頁 |
| 文件大?。?/td> | 915K |
| 代理商： | TLV2548MPWREP |
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SLAS668 – OCTOBER 2009
www.ti.com
An active CS, FS, or CSTART restores the device. There is no time delay when an external reference is
selected. However, if an internal reference is used, it takes about 20 ms to warm up. Deselect PWDN pin to
remove the device from the hardware power-down state. This requires about 20 ms to warm up if an internal
reference is also selected.
The configuration register is not affected by any of the power-down modes but the sweep operation sequence
has to be started over again. All FIFO contents are cleared by the power-down modes.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
Supply voltage range, GND to VCC
–0.3 to 6.5
V
Analog input voltage range
–0.3 to VCC + 0.3
V
Reference input voltage
VCC + 0.3
V
Digital input voltage range
–0.3 to VCC + 0.3
V
TJ
Operating virtual junction temperature range
–55 to 150
°C
TA
Operating free-air temperature range
–55 to 125
°C
Tstg
Storage temperature range
–65 to 150
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°C
(1)
Stresses beyond those listed under the absolute maximum ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the recommended
operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
TA < 25°C
DERATING FACTOR
TA = 125°C
PACKAGE
POWER RATING
ABOVE TA = 25°C
(1)
POWER RATING
20 PW
977 mW
7.8 mW/°C
195 mW
(1)
This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). Thermal resistance is not production tested and the
values given are for informational purposes only.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
3.3
5.5
V
Analog input voltage(1)
0
VCC
V
VIH
High level control input voltage
2.1
V
VIL
Low–level control input voltage
0.6
V
Delay time, delay from CS falling edge to FS rising edge
td(CSL–FSH)
0.5
SCLKs
(see Figure 17).
Delay time, delay from 16th SCLK falling edge to CS
td(SCLK–CSH)
rising edge (FS = 1), or 17th rising edge (FS is active)
0.5
SCLKs
(see Figure 17 and Figure 20).
Setup time, FS rising edge before SCLK falling edge
tsu(FSH–SCLKL
20
ns
(see Figure 17).
Hold time, FS hold high after SCLK falling edge
th(FSH–SCLKL)
30
ns
(see Figure 17).
twH(CS)
Pulse width, CS high time (see Figure 17 and Figure 20).
100
ns
twH(FS)
Pulse width, FS high time (see Figure 17).
0.75
1
SCLKs
SCLK cycle time
VCC = 3.0 V to 3.6 V
67
10000
tc(SCLK)
(see Figure 17 and
ns
VCC = 4.5 V to 5.5V
50
10000
(1)
When binary output format is used, analog input voltages greater than that applied to REFP convert as all ones (111111111111), while
input voltages less than that applied to REFM convert as all zeros (000000000000). The device is functional with reference down to 1 V.
(VREFP
VREFM 1); however, the electrical specifications are no longer applicable.
18
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2548-EP
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