參數(shù)資料
型號(hào)： TLV2548MPWREP
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝： GREEN, PLASTIC, TSSOP-20
文件頁數(shù)： 23/37頁
文件大小： 915K
代理商： TLV2548MPWREP
www.ti.com
SLAS668 – OCTOBER 2009
Table 2. TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
This terminal controls the start of sampling of the analog input from a selected multiplex
channel. Sampling time starts with the falling edge of CSTART and ends with the rising edge
of CSTART as long as CS is held high. In mode 01, select cycle, CSTART can be issued as
CSTART
14
I
soon as CHANNEL is selected which means the fifth SCLK during the select cycle, but the
effective sampling time is not started until CS goes to high. The rising edge of CSTART
(when CS = 1) also starts the conversion. Tie this terminal to VCC if not used.
End of conversion or interrupt to host processor. [PROGRAMMED AS EOC]: This output
goes from a high-to-low logic level at the end of the sampling period and remains low until
the conversion is complete and data are ready for transfer. EOC is used in conversion mode
00 only.
EOC/(INT)
4
O
xxx
[PROGRAMMED AS INT]: This pin can also be programmed as an interrupt output signal to
the host processor. The falling edge of INT indicates data are ready for output. The following
CS
↓ or FS clears INT.
DSP frame sync input. Indication of the start of a serial data frame in or out of the device. If
FS remains low after the falling edge of CS, SDI is not enabled until an active FS is
presented. A high-to-low transition on the FS input resets the internal 4-bit counter and
FS
17
I
enables SDI within a maximum setup time. SDI is disabled within a setup time after the 4-bit
counter counts to 16 (clock edges) or a low-to-high transition of CS whichever happens first.
xxx
Tie this terminal to VCC if not used. See the Data Code Information section, item 1.
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements
GND
15
I
are with respect to GND.
Both analog and reference circuits are powered down when this pin is at logic zero. The
PWDN
16
I
device can be restarted by active CS, FS or CSTART after this pin is pulled back to logic
one.
Input serial clock. This terminal receives the serial SCLK from the host processor. SCLK is
used to clock the input SDI to the input register. When programmed, it may also be used as
SCLK
3
I
the source of the conversion clock.
NOTE: This device supports CPOL (clock polarity) = 0, which is SCLK returns to zero when
idling for SPI compatible interface.
Serial data input. The input data is presented with the MSB (D15) first. The first 4-bit MSBs,
D(15
12) are decoded as one of the 16 commands. The configure write commands require
an additional 12 bits of data.
xxx
When FS is not used (FS =1), the first MSB (D15) is expected after the falling edge of CS
and is latched in on the rising edges of SCLK (after CS
↓).
SDI
2
I
xxx
When FS is used (typical with an active FS from a DSP) the first MSB (D15) is expected
after the falling edge of FS and is latched in on the falling edges of SCLK.
xxx
SDI is disabled within a setup time after the 4-bit counter counts to 16 (clock edges) or a
low-to-high transition of CS whichever happens first.
The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance
state when CS is high and after the CS falling edge and until the MSB is presented. The
output format is MSB first.
xxx
When FS is not used (FS = 1 at the falling edge of CS), the MSB is presented to the SDO
pin after the CS falling edge, and successive data are available at the rising edge of SCLK
and changed on the falling edge.
xxx
SDO
1
O
When FS is used (FS = 0 at the falling edge of CS), the MSB is presented to SDO after the
falling edge of CS and FS = 0 is detected. Successive data are available at the falling edge
of SCLK and changed on the rising edge. (This is typically used with an active FS from a
DSP.)
xxx
For conversion and FIFO read cycles, the first 12 bits are result from previous conversion
(data) followed by 4 don’t care bits. The first four bits from SDO for CFR read cycles should
be ignored. The register content is in the last 12 bits. SDO is 3-state (float) after the 16th bit.
See the Data Code Information section, item 2.
External reference input or internal reference decoupling. Tie this pin to analog ground if
REFM
18
I
internal reference is used.
Copyright 2009, Texas Instruments Incorporated
3
Product Folder Link(s): TLV2548-EP
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