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參數(shù)資料
| 型號： | TLV2548MPWREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 11/37頁 |
| 文件大?。?/td> | 915K |
| 代理商： | TLV2548MPWREP |
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SLAS668 – OCTOBER 2009
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Pulse width, SCLK low
VCC = 4.5 V
22
twL(SCLK)
time (see Figure 17 and
ns
VCC = 3.0 V
27
Pulse width, SCLK high
VCC = 4.5 V
22
twH(SCLK)
time (see Figure 17 and
ns
VCC = 3.0 V
27
Setup time, SDI valid before falling edge of SCLK (FS is
tsu(DI–SCLK
active) or the rising edge of SCLK (FS=1)
25
ns
(see and Figure 20).
Hold time, SDI hold valid after falling edge of SCLK (FS
th(DI–SCLK)
is active) or the rising edge of SCLK (FS=1)
5
ns
(see Figure 17).
Delay time, delay from CS falling edge to SDO valid
td(CSL–DOV)
25
ns
(see Figure 17 and Figure 20).
Delay time, delay from FS falling edge to SDO valid
td(FSL–DOV)
25
ns
(see Figure 17).
Delay time, delay from
SDO = 0 pF
0.5 SCLK + 5
VCC = 5.5 V
SCLK falling edge (FS is
SDO = 60 pF
0.5 SCLK + 24
active) or SCLK rising
SDO = 5 pF
0.5 SCLK + 12
edge (FS=1) to SDO valid
(see Figure 17 and
td(SCLK–DOV)
ns
VCC = 3.0 V
For a date code later than
SDO = 25 pF
0.5 SCLK + 33
xxx, see the Data Code
Information section, item
3.
Delay time, delay from 17th SCLK rising edge (FS is
active) or the 16th falling edge (FS=1) to EOC falling
td(SCLK–EOCL)
45
ns
edge
(see Figure 17 and Figure 20).
Delay time, delay from 16th SCLK falling edge to INT
td(SCLK–INTL)
falling edge (FS =1) or from the 17th rising edge SCLK
Min t(conv)
s
to INT falling edge (when FS active) (see Figure 20).
td(CSL–INTH)
Delay time, delay from CS falling edge or FS rising edge
or
50
ns
td(FSH–INTH)
and Figure 20).
Delay time, delay from CS rising edge to CSTART falling
td(CSH–CSTARTL)
100
ns
edge (see Figure 18 and Figure 19).
Delay time, delay from CSTART rising edge to EOC
td(CSTARTH–EOCL)
50
ns
falling edge (see Figure 18 and Figure 19).
Pulse width, CSTART low time (see Figure 18 and
twL(CSTART)
Min t(sample)
μs
Delay time, delay from CSTART rising edge to CSTART
td(CSTARTH–CSTARTL)
Max t(conv)
μs
falling edge (see Figure 19).
Delay time, delay from CSTART rising edge to INT
td(CSTARTH–INTL)
Max t(conv)
μs
falling edge (see Figure 18 and Figure 19).
TA
Operating free–air temperature
–55
125
°C
Copyright 2009, Texas Instruments Incorporated
19
Product Folder Link(s): TLV2548-EP
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