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參數(shù)資料
| 型號(hào)： | TLV2548MPWREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 8/37頁 |
| 文件大?。?/td> | 915K |
| 代理商： | TLV2548MPWREP |
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6
5
4
3
2
1
0
ADC
12-BITx8
FIFO
SDO
Serial
FIFO Full
FIFO 3/4 Full
FIFO 1/2 Full
FIFO 1/4 Full
FIFO Threshold Pointer
SLAS668 – OCTOBER 2009
www.ti.com
FIFO Operation
Figure 15. TLV2548 FIFO
The device has an eight-layer FIFO that can be programmed for different thresholds. An interrupt is sent to the
host after the pre-programmed threshold is reached. The FIFO can be used to store data from either a fixed
channel or a series of channels based on a pre-programmed sweep sequence. For example, an application may
require eight measurements from channel 3. In this case, the FIFO is filled with eight data sequentially taken
from channel 3. Another application may require data from channel 0, channel 2, channel 4, and channel 6 in an
orderly manner. Therefore, the threshold is set for 1/2 and the sweep sequence 0
2460246 is chosen.
An interrupt is sent to the host as soon as all four data are in the FIFO.
In single shot mode, the FIFO automatically uses a 1/8 FIFO depth. Therefore the CFR bits (D1,0) controlling
FIFO depth are don’t care.
SCLK and Conversion Speed
There are two ways to adjust the conversion speed.
The SCLK can be used as the source of the conversion clock to get the highest throughput of the device.
The minimum onboard OSC is 3.6 MHz and 14 conversion clocks are required to complete a conversion
(corresponding 3.86-
μs conversion time). The devices can operate with an SCLK up to 20 MHz for the supply
voltage range specified. When a more accurate conversion time is desired, the SCLK can be used as the
source of the conversion clock. The clock divider provides speed options appropriate for an application where
a high speed SCLK is used for faster I/O. The total conversion time is 14 x (DIV/fSCLK) where DIV is 1, 2, or 4.
For example a 20-MHz SCLK with the divide by 4 option produces a 14 x (4/20 M) = 2.8-
μs conversion time.
When an external serial clock (SCLK) is used as the source of the conversion clock, the maximum equivalent
conversion clock (fSCLK/DIV) should not exceed 6 MHz.
Autopower down can be used to slow down the device at a reduced power consumption level. This mode is
always used by the converter. If the device is not accessed (by CS or CSTART), the converter is powered
down to save power. The built-in reference is left on in order to quickly resume operation within one half
SCLK period. This provides unlimited choices to trade speed with power savings.
Reference Voltage
The device has a built-in reference with a programmable level of 2 V or 4 V. If the internal reference is used,
REFP is set to 2 V or 4 V and REFM should be connected to the analog ground of the converter. An external
reference can also be used through two reference input pins, REFP and REFM, if the reference source is
programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the
analog inputs to produce a full-scale and zero-scale reading respectively. The values of REFP, REFM, and the
analog input should not exceed the positive supply or be lower than GND consistent with the specified absolute
maximum ratings. The digital output is at full scale when the input signal is equal to or higher than REFP and at
zero when the input signal is equal to or lower than REFM.
16
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2548-EP
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