參數(shù)資料
型號(hào)： TLV320ADC3001IYZHR
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16
封裝： GREEN, DSBGA-16
文件頁(yè)數(shù)： 13/81頁(yè)
文件大?。?/td> 836K
代理商： TLV320ADC3001IYZHR
RD(n)
RD(n+1)
2
1
0
3
2
1
0
3
LD (n)
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3
Right Channel
Left Channel
Ch_Offset_1 = 0
Ch_Offset_2 = 1
LD(n)
LD(n+1)
2
1
0
3
2
1
0
3
RD (n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = nth Sample of Left-Channel Data
RD(n) = nth Sample of Right-Channel Data
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3
Ch_Offset_1 = 0
LD(n)
LD(n+1)
4
3
2
5
1
0
4
3
2
5
1
0
5
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = nth Sample of Left-Channel Data
RD(n) = nth Sample of Right-Channel Data
WORD
CLOCK
BIT
CLOCK
DATA
n-1
Ch_Offset_1 = 2
SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
MSB of the left channel is valid on the (Ch_Offset_2 + 1)th rising edge of the bit clock following the LSB of the
right channel. Figure 22 shows the operation in this mode with Ch_Offset_1 = 0 and Ch_Offset_2 = 1. The MSB
of the right channel is valid on the first rising edge of the bit clock after the rising edge of the word clock. Data
transfer for the left channel starts following the completion of data transfer for the right channel without waiting for
the falling edge of the word clock. The MSB of the left channel is valid on the second rising edge of the bit clock
after the LSB of the right channel.
Figure 22. Left-Justified Mode, Time-Slot-Based Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 1,
Channel Swapping Enabled
I2S Mode
In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock. Figure 23 shows the standard I2S timing.
Figure 23. I2S Mode (Standard Timing)
Figure 24 shows the I2S mode timing with Ch_Offset_1 = 2.
Figure 24. I2S Mode With Ch_Offset_1 = 2
20
Copyright
2008–2011, Texas Instruments Incorporated
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