參數(shù)資料
型號： TLV320ADC3001IYZHR
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16
封裝： GREEN, DSBGA-16
文件頁數(shù)： 61/81頁
文件大?。?/td> 836K
代理商： TLV320ADC3001IYZHR
SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
Page 1 / Register 58: Reserved
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
–D0
R
XXXX XXXX
Reserved. Do not write to this register.
Page 1 / Register 59: Left Analog PGA Settings
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
1
0: Left PGA is not muted.
1: Left PGA is muted.
D6
–D0
R/W
000 0000
000 0000: Left PGA gain = 0 dB
000 0001: Left PGA gain = 0.5 dB
000 0010: Left PGA gain = 1 dB
...
101 0000: Left PGA gain = 40 dB
101 0001
–111 1111: Reserved. Do not use.
Page 1 / Register 60: Right Analog PGA Settings
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
1
0: Right PGA is not muted
1: Right PGA is muted
D6
–D0
R/W
000 0000
000 0000: Right PGA gain = 0 dB
000 0001: Right PGA gain = 0.5 dB
000 010: Right PGA gain = 1 dB
...
101 0000: Right PGA gain = 40 dB
101 0001
–111 1111: Reserved. Do not use.
Page 1 / Register 61: ADC Low-Current Modes
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
–D1
R
0000 000
Reserved. Write only zeros to these bits.
D0
R/W
0
0: 1
× ADC modulator current used
1: 0.5
× ADC modulator current used
Page 1 / Register 62: ADC Analog PGA Flags
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
–D2
R
0000 00
Reserved. Do not write any value other than reset value.
D1
R
0
0: Left ADC PGA, applied gain
≠ programmed gain
1: Left ADC PGA, applied gain = programmed gain
D0
R
0
0: Right ADC PGA, applied gain
≠ programmed gain
1: Right ADC PGA, applied gain = programmed gain
Page 1 / Register 63 Through Page 1 / Register 127: Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
–D0
R
XXXX XXXX
Reserved. Do not write to these registers.
64
Copyright
2008–2011, Texas Instruments Incorporated
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TLV320ADC3001IYZHT 制造商:Texas Instruments 功能描述:Analog/Digital (A/D) Converter IC
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