參數(shù)資料
型號: TLV320ADC3001IYZHR
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16
封裝: GREEN, DSBGA-16
文件頁數(shù): 5/81頁
文件大?。?/td> 836K
代理商: TLV320ADC3001IYZHR
TLV320ADC3001
IN2 L
IN1 L (P)
MICBIAS
AVDD
AVSS
DVDD
DVSS
IOVDD
1.65 V–1.95 V
IOVDD
(1.1 V–3.3 V)
A
AVDD
(2.6 V–3.6 V)
S
D
A
S
C
L
IOVDD
M
C
L
K
B
C
L
K
W
C
L
K
D
O
U
T
DBB
IN1 R(M)
A
D
RESET
R
P
R
P
1mF
0.1
F
m
1 F
m
0.1
F
m
1 F
m
0.1
F
m
1 F
m
1 F
m
1 F
m
2 kW
1 F
m
SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
TYPICAL CIRCUIT CONFIGURATION
Figure 11. Typical Connections
OVERVIEW
The TLV320ADC3001 is a flexible, low-power, stereo audio ADC product with extensive feature integration,
intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment
applications. The product integrates a host of features to reduce cost, board space, and power consumption in
space-constrained, battery-powered, portable applications.
The TLV320ADC3001 consists of the following blocks:
Stereo audio multibit delta-sigma ADC (8 kHz
–96 kHz)
miniDSP for custom processing
Built-in processing blocks for selectable digital audio effects (3-D, bass, treble, midrange, EQ, de-emphasis)
Register configurable combinations of up to three single-ended or one differential and one single-ended audio
inputs
Fully programmable PLL with extensive ADC clock source and divider options for maximum end-system
design flexibility
16-ball wafer chip-scale package (YZH)
Communication to the TLV320ADC3001 for control is via a two-wire I2C interface. The I2C interface supports
both standard and fast communication modes.
HARDWARE RESET
The TLV320ADC3001 requires a hardware reset after power up for proper operation. After all power supplies are
at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not
performed, the TLV320ADC3001 may not respond properly to register reads/writes.
Copyright
2008–2011, Texas Instruments Incorporated
13
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