參數(shù)資料
型號: TLV320ADC3001IYZHR
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16
封裝: GREEN, DSBGA-16
文件頁數(shù): 2/81頁
文件大?。?/td> 836K
代理商: TLV320ADC3001IYZHR
WCLK
BCLK
DOUT
t (BCLK)
H
t (WS)
h
t (BCLK)
L
t (WS)
s
t (WS)
h
t (DO-BCLK)
d
t (WS)
h
tf
tr
(see NOTE)
-140
-120
-100
-80
-60
-40
-20
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Frequency-kHz
d
B
SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
All specifications at 25
°C, DVDD = 1.8 V
Note A. Falling edge inside a frame for WCLK is arbitrary inside frame.
IOVDD = 1.8 V
IOVDD = 3.3 V
PARAMETER
UNIT
MIN
MAX
MIN
MAX
tH(BCLK)
BCLK high period
35
ns
tL(BCLK)
BCLK low period
35
ns
ts(WS)
BCLK/WCLK setup time
10
8
ns
th(WS)
BCLK/WCLK hold time
10
8
ns
td(DO-BCLK)
BCLK to DOUT delay time
25
20
ns
tr
Rise time
15
8
ns
tf
Fall time
15
8
ns
NOTE: All timing specifications are measured at characterization.
Figure 5. DSP Timing in Slave Mode
TYPICAL CHARACTERISTICS
Figure 6. Line Input to ADC FFT Plot
10
Copyright
2008–2011, Texas Instruments Incorporated
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