參數(shù)資料
型號： TLV320AIC21I
廠商： Texas Instruments, Inc.
英文描述： Layout and Grounding Guidelines for TLV320AIC2x
中文描述： 為TLV320AIC2x布局和接地指南
文件頁數(shù)： 16/46頁
文件大?。?/td> 452K
代理商： TLV320AIC21I
SLAS428 AUGUST 2004
www.ti.com
16
AUDIO DATA CONVERTERS
The ’DAC26 has a stereo audio DAC. The DAC can operate with a maximum sampling rate of 53 kHz and support all audio
standard rates of 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz. By utilizing the
flexible clock generation capability and internal programmable interpolation, a wide variety of sampling rates up to 53 kHz
can be obtained from many possible MCLK inputs.
When the DAC is operating, the ’DAC26 requires an applied audio MCLK input
.
The user should also set
bit D13/REG06H/Page2 to indicate which Fsref rate is being used.
Typical audio DACs can suffer from poor out-of-band noise performance when operated at low sampling rates, such as
8 kHz or 11.025 kHz. The ’DAC26 includes programmable interpolation circuitry to provide improved audio performance
at such low sampling rates, by first upsampling low-rate data to a higher rate, filtering to reduce audible images, and then
passing the data to the internal DAC, which is actually operating at the Fsref rate. This programmable interpolation is
determined using bit D5D3/REG00H/Page2.
For example, if playback of 11.025-kHz data is required, the ’DAC26 can be configured such that Fsref = 44.1 kHz. Then
using bit D5D3/REG00H/Page2, the DAC sampling rate (Fs) can be set to Fsref/4, or Fs = 11.025 kHz. In operation, the
11.025-kHz digital input data is received by the ’DAC26, upsampled to 44.1 kHz, and filtered for images. It is then provided
to the audio DAC operating at 44.1 kHz for playback. In reality, the audio DAC further upsamples the 44.1 kHz data by a
ratio of 128x and performs extensive interpolation filtering and processing on this data before conversion to a stereo analog
output signal.
PLL
The ’DAC26 has an on-chip PLL to generate the needed internal DAC operational clocks from a wide variety of clocks
available in the system. The PLL supports an MCLK varying from 2 MHz to 50 MHz and is register programmable to enable
generation of required sampling rates with fine precision.
DAC sampling rates are given by
DAC_FS = Fsref/N1
where, Fsref must fall between 39 kHz and 53 kHz, and N1, N2 =1, 1.5, 2, 3, 4, 5, 5.5, 6 are register programmable.
The PLL can be enabled or disabled using register programming.
When PLL is disabled
Fsref
MCLK
128
Q
Q = 2, 3
…
17
In this mode, the MCLK can operate up to 50 MHz, and Fsref should fall within 39 kHz to 53 kHz.
When PLL is enabled
Fsref
MCLK
2048
K
P
P = 1, 2, 3,
…
, 8
K = J.D
J = 1, 2, 3,
…
.,64
D = 0, 1, 2,
…
, 9999
P, J, and D are register programmable, where J is an integer part of K before the decimal point, and D is a four-digit fractional
part of K after the decimal point, including lagging zeros.
Examples:
If K = 8.5, Then J = 8, D = 5000
If K = 7.12, Then J = 7, D = 1200
If K = 7.012, Then J = 7, D = 120
The PLL is programmed through Registers 1BH and 1CH of Page2.
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