TLV320AIC27
STEREO AUDIO CODEC
SLAS253A – MARCH 2000 – REVISED SEPTEMBER 2000
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ac-link digital serial interface protocol (continued)
The data streams currently defined by the AC’97 specification include:
PCM playback—two output slots
Two-channel composite PCM output stream
PCM record data—two input slots
Two-channel composite PCM input stream
Control—two output slots
Control register write port
Status—two input slots
Control register read port
Optional dedicated microphone input—one input slot
Dedicated microphone input stream in support of stereo AEC
and/or other voice applications
Optional modem line codec output—one output slot
Modem line codec DAC input stream
Optional modem line codec input—one input slot
Modem line codec ADC output stream
The TLV320AIC27 controller signals synchronization of all ac-link data transactions. The TLV320AIC27 drives
the serial bit clock onto the ac link, which the AC’97 controller then qualifies with a synchronization signal to
construct audio frames.
SYNC, fixed at 48 kHz, is derived by dividing down the serial clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz,
provides the necessary clocking granularity to support 12 20-bit outgoing and incoming time slots. Ac-link serial
data transition occurs on each rising edge of BIT_CLK. The receiver of ac-link data (TLV320AIC27 for outgoing
data and AC’97 controller for incoming data) samples each serial bit on the falling edges of BIT_CLK.
The ac-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid tag for its
corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0 indicates that the
corresponding time slot within the current audio frame has been assigned to a data stream and contains valid
data. If a slot is tagged invalid, it is the responsibility of the data source (the TLV320AIC27 for the input stream
and the AC’97 controller for the output stream) to fill all bit positions with 0s during that slot’s active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame.
The portion of the audio frame where SYNC is high is defined as the tag phase. The remainder of the audio frame
where SYNC is low is defined as the data phase. Additionally, all clock, sync, and data signals can be halted
to save power. This requires that the TLV320AIC27 be implemented as a static design to allow its register
contents to remain intact when entering a power savings mode.
ac-link audio output frame (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting
the TLV320AIC27’s DAC inputs and control registers. As mentioned earlier, each audio output frame supports
up to 12 20-bit outgoing data time slots. Slot 0 is a reserved time slot containing 16-bits, which are used for
ac-link protocol infrastructure.
The first bit within slot 0 is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the entire audio
frame. A valid frame bit equal to 1 indicates that the current audio frame contains at least one time slot of valid
data. The next 12-bit positions sampled by the TLV320AIC27 indicate which of the corresponding 12 time slots
contain valid data.
In this way, data streams of differing sample rates can be transmitted across the ac link at its fixed 48-kHz audio
frame rate. Figure 9 illustrates the time-slot-based ac-link protocol.